Backside Gate Tie-Down Layout for Smaller Standard Cells
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Solution Overview
Problem
Conventional gate-tie-down (GTD) schemes in integrated circuit technology face challenges with scaling as they require wider power rails and larger logic cells due to frontside power designs, making it difficult to achieve electrical diffusion break without physical diffusion break, which increases parametric variation and is undesirable.
Innovation Solution
The implementation of a backside power (BSP) trench contact jumper tie-down (TCJTD) scheme, where a nano ribbon is formed within the gate, and backside power rails are placed below the gate and nano ribbon, with a jumper contact electrically coupling the gate to the backside and frontside contacts to apply a turn-off voltage, enabling electrical diffusion break without physical breakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional frontside power GTD schemes are used, then electrical diffusion break is achieved, but power rail width and logic cell size increase
Solution Approach 1:
The patent moves the power rail from the frontside (2D plane) to the backside of the semiconductor device, utilizing the third dimension (depth/vertical stacking). The backside power rail is positioned beneath the substrate, allowing electrical diffusion break to be achieved without occupying additional lateral space in the logic cell, thereby reducing the logic cell area while maintaining electrical isolation functionality.
Solution Approach 2:
The gate structure is designed to physically contain the diffusion region within its boundaries. The diffusion break is achieved by nesting the diffusion region inside the gate structure, where the gate material itself acts as the diffusion barrier. This eliminates the need for separate diffusion break structures and reduces overall cell size.
2Reliability
If frontside power GTD schemes are used, then electrical diffusion break is achieved, but power rail width increases
Solution Approach 1:
The power rail is relocated from the frontside horizontal plane to the backside vertical plane of the substrate. This dimensional shift allows the power rail to extend in the lateral direction without increasing the device footprint, as it is now positioned beneath the substrate rather than alongside the diffusion region. The backside power rail achieves electrical diffusion break with minimal width requirement.
3Productivity
If smaller logic cells are used, then area scaling is improved, but achieving GTD becomes difficult
Solution Approach 1:
By moving the power rail delivery path to the backside of the substrate, the patent enables GTD functionality in compact logic cells without requiring additional lateral space. The backside power rail can be routed to contact regions beneath the substrate, allowing GTD to be implemented in smaller cells while maintaining ease of manufacture through standard backside contact fabrication processes.
Solution Approach 2:
Instead of delivering power to the gate from the frontside through lateral power rails, the patent inverts the approach by delivering power from the backside through vertical connections. This inversion allows the power delivery path to be separated from the lateral diffusion region, enabling GTD in smaller cells without complicating the manufacturing process.
Data Source
AI summary
Disclosed are gate-tie-down (GTD) cells that utilize a backside power delivery scheme, where metal wires that deliver power are provided on the back of the die. The backside power may be delivered to the gates through S/Ds and through frontside contacts. As a result, ultra-low height standard cell can be enabled. Also higher area scaling may be achieved. Further, performance and power gain can be maximized.