3D Memory Cell Layout for Parallel Read and Lower Disturbance
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Solution Overview
Problem
Conventional 3D vertical channel semiconductor devices have low operation speed, high power consumption, and significant gate disturbance due to the need for multiple selection line cycles and unnecessary power usage in non-selected strings.
Innovation Solution
A 3D semiconductor device design where all cells can be read simultaneously, with vertically stacked memorygate layers, parallel selection lines, and bit lines, allowing adjacent cells in the same column to be electrically connected to different bit lines, reducing power consumption and gate disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional cell design with multiple selection line cycles is used, then all cell data can be read, but operation speed is low and power consumption is high
Solution Approach 1:
The patent segments the bit lines into multiple groups (first group, second group, third group, fourth group) and assigns different selection lines to control different groups. This allows simultaneous reading of cells connected to different bit line groups by applying different selection line voltages, thereby increasing operation speed and reducing power consumption by avoiding sequential cycling through all selection lines.
Solution Approach 2:
The patent applies partial action by selectively activating only the necessary selection lines and bit line groups for each reading operation. Instead of cycling through all selection lines to read all cells, the system reads only the required portions using specific combinations of selection lines and bit line groups, reducing unnecessary power consumption and operation cycles.
2Productivity
If conventional cell design with multiple selection line cycles is used, then all cell data can be read, but bandwidth is limited
Solution Approach 1:
The patent segments bit lines into multiple groups and associates each group with specific selection lines. This segmentation enables parallel reading operations where multiple bit line groups can be activated simultaneously with different selection line voltages, significantly increasing bandwidth and reducing the time required to read all cell data.
Solution Approach 2:
The patent enables continuous useful action by allowing multiple reading operations to proceed simultaneously through different selection line and bit line group combinations. Instead of sequential reading that loses time between cycles, the system maintains continuous data retrieval across multiple parallel channels, maximizing bandwidth utilization.
3Ease of operation
If conventional cell design with gate bias on all selection lines is used, then cell selection is achieved, but gate disturbance occurs in non-selected strings
Solution Approach 1:
The patent segments the control of selection lines by grouping bit lines and assigning specific selection lines to specific groups. This segmentation allows precise control where only the selection lines corresponding to active bit line groups are activated, while other selection lines remain at lower voltages. This eliminates gate disturbance in non-selected strings while maintaining ease of operation for cell selection.
4Ease of operation
If conventional cell design activates all selection lines is used, then cell selection is achieved, but unnecessary power consumption occurs in non-selected strings
Solution Approach 1:
The patent segments the selection line activation by grouping bit lines and selectively activating only the selection lines corresponding to active bit line groups. This segmentation eliminates unnecessary power consumption in non-selected strings while preserving the cell selection capability, as each selection line group can independently control its associated bit line groups.
Solution Approach 2:
The patent applies partial action by activating only the necessary selection lines and bit line groups for each reading operation. Instead of applying gate bias to all selection lines, the system activates only the portion needed for the current operation, significantly reducing unnecessary power consumption while maintaining full cell selection capability.
Data Source
AI summary
A 3D semiconductor device is provided, comprising plural memory layers vertically stacked on a substrate and parallel to each other; plural selection lines disposed on the memory layers and parallel to each other; plural bit lines disposed on the selection lines, and the bit lines arranged in parallel to each other and in perpendicular to the selection lines; plural strings formed vertically to the memory layers and the selection lines, and the strings electrically connected to the corresponding selection lines; a plurality of cells respectively defined by the strings, the selection lines and the bit lines correspondingly, and the cells arranged in a plurality of rows and columns, wherein a column direction is parallel to the bit lines while a row direction is parallel to the selection lines. The adjacent cells in the same column are electrically connected to the different bit lines.