3D Flash Memory Read Verification with Fast Charge Removal
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Solution Overview
Problem
In 3D NAND flash memory, fast charges trapped in shallow traps are easily lost, leading to inefficient read-verification operations due to long de-trapping processes, which affect the accuracy of threshold voltage determination and increase bit-error-rates.
Innovation Solution
A read-verification operation is implemented with a read-prepare step that applies a prepare voltage on an unselected top select gate and a pass voltage on unselected word lines to accelerate fast charge loss, followed by a sensing step to measure the threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional read verification is used in 3D memory devices, then read operations can be performed, but read verification failures occur due to interference from fast charges in unselected memory cells
Solution Approach 1:
The patent applies preliminary anti-action by removing fast charges from unselected memory cells before performing the read verification operation. The read-prepare step applies specific voltages to unselected word lines and select gates to discharge fast charges that would otherwise interfere with the read operation, thereby preventing read verification failures caused by charge interference from neighboring cells
Solution Approach 2:
The patent extracts the harmful fast charges from unselected memory cells through the read-prepare step. By applying voltages that selectively remove fast charges from unselected cells while preserving data in selected cells, the interference source is separated and removed from the system before the read operation proceeds
2Reliability
If read-prepare step is added to remove fast charges, then read verification accuracy improves, but operation complexity increases
Solution Approach 1:
The patent merges the fast charge removal function with the existing read operation sequence. The read-prepare step is integrated into the read pipeline as a preliminary stage that uses the same voltage application infrastructure (word lines and select gates) already present in the memory device, combining charge removal with the read operation rather than adding separate dedicated removal circuitry
Solution Approach 2:
The patent makes the word lines and select gates multi-functional by using them for both data storage/access and fast charge removal. The same voltage application mechanisms used for normal read operations are repurposed to perform the read-prepare function, eliminating the need for separate dedicated charge removal circuitry and reducing overall device complexity
3Reliability
If multiple voltage levels are applied during read-prepare, then fast charge removal effectiveness improves, but energy consumption increases
Solution Approach 1:
The patent uses periodic voltage application in the read-prepare step, where voltages are applied in specific sequences and time intervals to efficiently remove fast charges. The voltages are applied periodically rather than continuously, allowing charge removal to occur in controlled bursts that are energy-efficient while maintaining effectiveness
Solution Approach 2:
The patent changes voltage parameters (magnitude, duration, timing) of the read-prepare step to optimize the balance between charge removal effectiveness and energy consumption. By carefully controlling voltage levels and application timing, the patent achieves effective fast charge removal while minimizing the energy required for the operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method stabilizes the threshold voltage of memory cells, reducing read disturb and shortening the read-prepare step duration, thereby improving the accuracy and efficiency of read-verification operations.
Implementation Method 1
a charge trap layer comprising first trapped charges associated with a first set of programming pulses and second trapped charges associated with a second set of programming pulses
Implementation Method 2
measuring a threshold voltage of the target memory cell at a sensing step
Data Source
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AI summary
A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device includes removing fast charges of the target memory cell at a read-prepare step and measuring a threshold voltage of the target memory cell at a sensing step. Removing the fast charges of the target memory cell includes applying a prepare voltage (Vprepare) on an unselected top select gate (Unsel_TSG) of an unselected memory string, applying a first off voltage (Voff) on a selected word line (Sel_WL) associated with the target memory cell, and applying a pass voltage (Vpass) on an unselected word line (Unsel _WL).