Read-Only Memories TRIZ Cases

Protecting layers block silicide spike formation on n-doped regions, reducing program disturbance and improving antifuse memory programming reliability.

Simultaneous write and layer-by-layer read testing cuts 3D memory array test time while preserving failed-cell detection and spare use.

A control circuit and paired latches let one flash plane read while another is programmed, cutting sequential command overhead.

Grouped wordlines use cell-size and neighbor-level offsets to correct program verify voltage, reducing bit errors and preserving read window budget.

All-levels programming with corrective verify offsets cuts memory programming time while compensating for adjacent wordline interference.

Different pass voltages on upper and lower dummy word lines curb program disturbance in 3D memory and improve programming reliability.

State-specific fail bit count thresholds let memory verify loops stop earlier, improving program speed while preserving threshold voltage margins.

By detecting voltage thresholds, the controller switches to fast programming to save designated data before capacitor power runs out.

Staggered discharge of erased, programmed, and dummy wordlines speeds 3D NAND verify recovery while preventing disturb and unstable channel boosting.

Catalytic nickel crystallization reduces silicon grain boundaries in stacked oxide-semiconductor memory cells, improving speed, density, and reliability.

Distributed memory sub-block access spreads simultaneous cell reads across the array to reduce current imbalance, supply noise, and reference disturbance.

A read-prepare voltage scheme removes fast charges before sensing in 3D flash memory, improving threshold voltage accuracy and read efficiency.

A staged word-line and selection-line voltage sequence controls write-stop transitions to limit threshold variation and preserve read accuracy.

Multiple timed reads and cell-specific threshold models reduce random telegraph noise errors in NAND flash and improve read accuracy.

Sub-block erase biasing in 3D NAND protects boundary word-lines from deep and soft erase, improving threshold stability and erase reliability.

Time-based sensing reads variable-impedance memory cells more accurately, enabling multi-bit storage and faster data retrieval.

Controlled source-line ramping and staged word-line biasing boost GIDL erase current, speeding NAND memory erasure while preserving reliability.

In-plane word-line contacts, symmetric decoder layout, and a buried source line shorten paths, reduce layout complexity, and raise 3D flash density.

Adaptive strobe gating uses incoming timing events to frame active edges and block overhead edges under skew and tight burst spacing.

Insulation bridges support adjacent 3D memory blocks, preserving high integration density while limiting deformation and electrical interference.

Checks and recovers drain, source, and central switch transistors during erase and program margins to sustain memory I/O reliability.

Shifted threshold voltage distributions guide flash read voltages, reducing bit errors and improving data retrieval after disturbance.

By tracking write temperature and checking read temperature, the controller sets block read thresholds to cut read retries and latency.

Different bit line precharge levels for read and verify operations improve flash memory program accuracy and reduce verify inefficiency.

Segmented insulating layers in the interposed region help control deep pillar etching, improving manufacturability and electrical stability in stacked memory.

Reference memory cells generate a PVT-tracking signal that improves sensing margins in high-density 3D memory without high-voltage circuits.

A self-referencing MRAM OTP write scheme detects breakdown onset and adds pulses until MTJ current saturation confirms hard, stable breakdown.

Multi-stage charging switches word or bit lines from a first voltage to a second after a reference condition, cutting 3D memory power use.

Optical annealing and heat-spreading layers enable dense 3D transistor stacking while protecting metal interconnects and improving power delivery.

Two-stage in-situ steam and thermal oxidation builds thick gate oxide while preserving uniform SONOS charge traps for MLC and high-voltage integration.

Suspending NAND erase voltage at selected waveform phases lets SSDs insert other operations without adding excess erase time or cell stress.

Periodic reference time and voltage updates help a memory searching engine maintain accurate Hamming-distance searches despite 3D flash drift.

Grouping 3D NAND cells by interference level enables tailored read voltages that reduce bit errors and improve storage reliability.

FLASH cells perform matrix-vector multiplication in memory, cutting data-transfer energy and hardware overhead in deep neural networks.

Dynamic temperature-range compensation adjusts memory read parameters to cut read errors and avoid latency from repeated error handling.

Two-stage boundary detection distinguishes partially erased from partially written memory blocks after power loss in non-uniform erase schemes.

When latch setting data is corrupted by soft errors, the controller compares it with reference values and resets the latch without restarting.

Selective switching between external and charge-pump voltage cuts programming errors, power use, and throughput loss in semiconductor memory.

Deck-aware block allocation steers programming away from high-RBER wordlines, reducing ECC decoding, latency, and host timeouts.

Dummy word lines route multiple memory blocks to separate sense amplifiers, cutting scan time without overlapping read data.

Temperature-shaped delay bias adjusts VTC compensation timing, preserving memory sense margins across changing thermal conditions.

GIDL-based string selection enables selective erase in nonvolatile memory, improving threshold voltage distribution and erase inhibition efficiency.

A mid-plane staircase layout shortens drive-current paths in 3D NAND, cutting resistance and RC delay as layer dimensions shrink.

Extended threshold-voltage sensing identifies the true slow memory plane before early termination, reducing program disturb and data corruption.

Stacked memory cells over periphery circuits use oxide and metal bonding to shorten wiring, lower access energy, and increase density.

A paired sub-memory cell layout boosts sensing margin by comparing bit-line currents, improving non-volatile memory read reliability.

A gate-last 3D NAND structure improves channel-to-conductor tier coupling, supporting reliable vertical memory strings and robust fabrication.

Cross-coupled inverter feedback reads blown and unblown fuse states at low voltage and current, fitting energy-harvesting power limits.

Shared gates and a wall-supported N/P cell array improve anti-fuse OTP programming stability for secure key and code storage.

A shared global counter replaces local ADCs in memory sensing circuits, cutting area and power while preserving current-difference readout.