3D Memory Stack Interposer Layout for Uniform Pillar Etching

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Solution Overview

Problem

Existing semiconductor memory devices face challenges in manufacturability due to complex stacked structures of word lines and insulating layers, which affect production efficiency and reliability.

Innovation Solution

The semiconductor memory device incorporates a unique stacked body configuration with alternating layers of conductive and insulating materials, featuring a connection portion with varying widths and a thicker interposed portion to enhance manufacturability and electrical connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If high aspect ratio hole etching is performed to form memory pillars through stacked bodies, then vertical integration and storage density are improved, but etching rate decreases and manufacturing precision deteriorates

Engineering Contradiction:

Improvestorage densityVSAvoidetching uniformity

Core Design Contradiction:

Volume of moving objectVSManufacturing precision

Solution Approach 1:

The stacked body is divided into multiple sections with insulating layers segmented into first, second, and third layers. This segmentation allows differential etching control at different depths, maintaining etching uniformity while achieving high vertical integration for increased storage density.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The third insulating layer acts as an intermediary stopper layer that regulates etching depth. By positioning this layer between the first and second insulating layers, it mediates the etching process to prevent over-etching and maintains manufacturing precision in high aspect ratio structures.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If staircase multistage processing is performed to form conductive layers at different heights, then device functionality is improved, but process complexity increases and pitch uniformity deteriorates

Engineering Contradiction:

Improvedevice functionalityVSAvoidprocess complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

Different insulating layers are positioned at different horizontal positions to create local quality variations. The first insulating layer extends to a first horizontal position, the second to a second horizontal position, and the third to a third horizontal position, enabling staircase multistage processing with improved pitch uniformity while maintaining device functionality.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The insulating layers are formed in advance with predetermined horizontal extensions before conductive layers are deposited. This preliminary action establishes the staircase structure geometry early in the process, simplifying subsequent processing steps and reducing overall process complexity.

Inventive Principle:

Principle #10Preliminary action

3Manufacturing precision

If additional insulating layers are added to control etching depth, then manufacturing precision is improved, but electrical performance may deteriorate due to increased insulation interference

Engineering Contradiction:

Improveetching depth controlVSAvoidelectrical performance

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The third insulating layer is positioned to extend only to a third horizontal position that is more limited than the first and second horizontal positions. This parameter change in spatial extent allows the layer to control etching depth while minimizing its electrical influence on memory pillars and conductive layers, thereby maintaining electrical performance.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12626764B2Semiconductor memory device and method of manufacturing semiconductor memory device

Publication Date: 2026.05.12 KIOXIA CORP

AI summary

A semiconductor memory device includes a first stacked body, a second stacked body, an interposed portion, and a columnar body. The interposed portion is disposed between the first stacked body and the second stacked body. The columnar body includes a first columnar portion extending in a first direction inside the first stacked body, a second columnar portion extending in the first direction inside the second stacked body, and a connection portion disposed in the interposed portion and connecting the first columnar portion to the second columnar portion. At least part of the interposed portion has a first layer containing a first insulating material, a second layer disposed between the first layer and the second stacked body in the first direction and containing the first insulating material, and a third layer disposed between the first layer and the second layer in the first direction and containing a first material different from the first insulating material.