Memory Cell Programming Verify Offsets for Wordline Interference
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Solution Overview
Problem
Existing memory devices face inefficiencies in programming time (Tprog) and reliability issues due to cell-to-cell interference, leading to widened threshold voltage distributions and reduced read window budget (RWB), especially in high-density memory devices.
Innovation Solution
Implementing an all levels program (ALP) operation integrated with corrective program verify (CPV) operations, where all programming levels are programmed simultaneously, followed by a corrective program verify operation that adjusts program verify voltage based on neighboring cell information to compensate for cell-to-cell coupling, thereby optimizing RWB and reducing programming time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential programming of levels is used, then programming can be completed with standard verify operations, but programming time is extended and energy consumption increases
Solution Approach 1:
The patent combines multiple programming levels into a single all-levels programming operation, allowing all levels to be programmed simultaneously rather than sequentially. This merging of operations reduces the total programming time while maintaining verification accuracy through integrated corrective verify operations.
Solution Approach 2:
The patent performs preliminary all-levels programming before executing corrective verify operations. By programming all levels in advance and then applying corrective verify operations with adjusted PV voltages, the system optimizes the programming process efficiency without compromising verification reliability.
2Reliability
If sequential programming of levels is used, then each level can be verified individually, but energy consumption and peak current levels increase
Solution Approach 1:
The patent merges individual level programming operations into a single all-levels programming operation, reducing the cumulative energy consumption and peak current levels associated with multiple sequential programming cycles. The combined operation is more energy-efficient while maintaining programming accuracy through corrective verify operations.
3Reliability
If sequential programming of levels is used, then programming can be performed with standard verify operations, but cell-to-cell interference causes threshold voltage distribution widening
Solution Approach 1:
The patent changes the PV voltage parameter by applying offsets based on the programming levels of subsequent neighbor wordlines. This parameter adjustment compensates for cell-to-cell interference effects, preventing threshold voltage distribution widening while maintaining programming operation stability and reliability.
4Productivity
If all levels are programmed together, then programming time and energy are reduced, but cell-to-cell interference effects occur
Solution Approach 1:
The patent addresses cell-to-cell interference by dynamically adjusting PV voltage offsets based on the programming levels of subsequent neighbor wordlines. This parameter modification allows all levels to be programmed together efficiently while compensating for interference effects, thus maintaining both productivity and reliability.
Solution Approach 2:
The patent implements a feedback mechanism where the programming levels of subsequent neighbor wordlines are used to determine appropriate PV voltage offsets. This feedback loop enables real-time compensation for cell-to-cell interference, allowing efficient all-levels programming without sacrificing threshold voltage distribution precision.
Data Source
AI summary
A memory device including a memory array including a set of target memory cells connected to a target wordline; and a first wordline adjacent to the target wordline, wherein the first wordline is to be programmed immediately subsequent to the target wordline; and control logic, operatively coupled with the memory array, to perform operations including causing, during a first time period of a program operation, a ramping wordline voltage to be applied to the set of target memory cells of the target wordline; causing, during the first time period, a disconnection of a set of pillars associated with the set of memory cells from a voltage supply and ground voltage, wherein each pillar corresponds to a respective programming level of a set of programming levels; causing, during a second time period of the program operation, a programming pulse to be applied to the set of target memory cells, wherein the programming pulse programs each programming level of the set of programming levels associated with the set of target memory cells; identify, based on programming level information of the first wordline, a program verify (PV) voltage offset associated with the target wordline; and causing, during a program verify time period of the program operation, a program verify voltage to be applied to the target wordline to verify programming of the set of target memory cells to a target programming level, wherein the program verify voltage is adjusted by the PV voltage offset.