Memory String Switch Transistor Recovery for Reliable I/O
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Solution Overview
Problem
Existing memory devices face challenges in maintaining efficient data input/output performance due to deterioration of switch transistors, leading to operational errors and reduced reliability.
Innovation Solution
Implementing check and recovery operations for the operating states of plural switch transistors, including drain select, source select, and central switching transistors, during operation margins of erase and program operations, with control circuitry managing these processes to maintain optimal transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If check and recovery operations are performed on switch transistors during data input/output operations, then operational reliability is improved, but device complexity increases due to additional control circuitry and operation margins
Solution Approach 1:
The control circuitry performs check operations on switch transistor operating states during operation margins before actual data input/output operations begin. This preliminary checking allows the system to detect and recover from transistor state deterioration in advance, ensuring reliable operation without adding complexity to the core data path.
Solution Approach 2:
The memory device performs self-diagnosis and self-recovery by automatically checking the operating states of switch transistors and executing recovery operations when deterioration is detected. This self-service mechanism maintains reliability without requiring external intervention or additional complex control systems.
2Productivity
If check and recovery operations are performed on switch transistors, then data input/output performance is improved, but loss of time occurs due to additional operation margins required
Solution Approach 1:
The control circuitry performs check operations periodically during operation margins at scheduled intervals rather than continuously. This periodic checking approach maintains transistor reliability while minimizing the time lost to check operations, as the margins are utilized efficiently without extending overall operation duration.
Solution Approach 2:
The check and recovery operations are integrated into existing operation margins without interrupting the continuous flow of data input/output operations. The useful action of data processing continues uninterrupted while check operations occur in the background during allocated margin periods, maintaining overall system productivity.
Data Source
AI summary
A memory device includes a cell array and control circuitry. The cell array includes plural memory cells and plural switch transistors. The control circuitry is configured to perform checking and recovery operations regarding operating states of the plural switch transistors during operation margins set for the plural data input/output operations.