Memory Verify Loop Control Using State-Specific Fail Bit Counts
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Solution Overview
Problem
Existing non-volatile memory systems face challenges in balancing threshold voltage budget and programming performance during memory cell verification due to tradeoffs between verify levels.
Innovation Solution
A memory apparatus and method that applies verification pulses of varying program verify voltages to memory cells and counts the number of cells below each threshold, terminating verify loops when a predetermined count threshold is reached for each data state, with different thresholds for different data states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single verify level is used for all memory cells, then the verification process is simple, but programming performance deteriorates due to inability to optimize for different data states
Solution Approach 1:
The patent segments the verification process by implementing separate verify loops for different data states (e.g., S1, S2, S3 states). Each verify loop uses data-state-specific parameters including tailored verify voltages and individual fail bit count thresholds. This segmentation allows optimized verification for each data state without requiring a single complex verify loop, thereby improving programming performance while maintaining manageable complexity through modular organization.
Solution Approach 2:
The patent introduces dynamic termination criteria for verify loops based on data-state-specific fail bit count thresholds. The verification process dynamically adapts by terminating early when the count of memory cells below the verify voltage threshold exceeds the predetermined threshold for that specific data state. This dynamic approach optimizes programming performance by avoiding unnecessary verification iterations while maintaining reliability.
2Productivity
If verify loops are terminated early to improve programming speed, then productivity increases, but reliability deteriorates due to potential incomplete verification
Solution Approach 1:
The patent applies local quality by establishing data-state-specific fail bit count thresholds rather than using a uniform threshold across all data states. Each data state (S1, S2, S3) has its own predetermined threshold value tailored to its characteristics. This localized approach ensures that early termination decisions are made with appropriate reliability criteria for each specific data state, maintaining verification accuracy while enabling speed optimization.
Solution Approach 2:
The patent changes verification parameters dynamically based on the data state being verified. Different verify voltages and different fail bit count thresholds are applied depending on which data state the memory cells are targeted for. This parameter adaptation allows the system to terminate verify loops early with confidence in reliability, as the termination criteria are specifically calibrated for each data state's verification requirements.
Data Source
AI summary
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to data states. A control means applies verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines and counts the memory cells having the threshold voltage below each of the program verify voltages targeted for each of the memory cells being programmed during each of a plurality of verify loops of a program-verify operation. The control means terminates the plurality of verify loops for the memory cells targeted for one of the data states in response to the count of the memory cells exceeding a predetermined count threshold. The predetermined count threshold is different for at least one of the data states compared to other ones of the data states.