3D Memory Cell Array Testing with Simultaneous Write-Read
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor integrated circuits become smaller and more complex, the resistance of conductive lines affects operating voltages and overall IC performance, necessitating efficient testing methods for memory cells in 3D memory cell arrays.
Innovation Solution
A method for testing 3D memory cell arrays involves simultaneously writing data to and performing read operations on each layer of memory cells, allowing for the identification and replacement of failed cells with spare cells, thereby reducing testing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional sequential testing methods are used on 3D memory cell arrays, then testing thoroughness is maintained, but testing time increases significantly
Solution Approach 1:
The 3D memory cell array is divided into multiple layers, and each layer is tested independently using separate word lines and read circuits. This segmentation allows parallel testing of different layers simultaneously, reducing overall testing time while maintaining thoroughness through layer-by-layer verification.
Solution Approach 2:
The patent transitions from traditional two-dimensional memory testing to three-dimensional memory testing by adding the vertical layer dimension. Multiple layers are accessed simultaneously using stacked word lines (WL0, WL1, WL2) and corresponding read circuits, enabling parallel operations across the vertical dimension to reduce testing time.
2Productivity
If simultaneous read operations are performed on all layers, then testing efficiency improves, but voltage control complexity increases
Solution Approach 1:
The voltage control system is segmented into layer-specific control circuits, with each read circuit (RC0, RC1, RC2) managing voltages for its corresponding layer. This segmentation allows independent voltage optimization for each layer while enabling simultaneous operations, reducing the complexity of unified voltage management.
Solution Approach 2:
Word lines are pre-charged to specific voltages before read operations begin, and select lines are pre-configured to activate only the required layers. This preliminary preparation reduces the complexity of real-time voltage switching during simultaneous read operations across multiple layers.
3Reliability
If spare memory cells are used to replace failed cells, then reliability improves, but device complexity increases
Solution Approach 1:
Spare memory cells are designed with multi-functionality, serving as replacement cells for failed cells in any layer. The spare cells share common bit lines and read circuit interfaces with regular cells, allowing them to assume multiple roles without requiring dedicated replacement structures for each layer, thus limiting the increase in device complexity.
Data Source
AI summary
A method of testing a three dimensional (3D) memory cell array includes applying a first voltage to word lines of each layer of memory cells in the 3D memory cell array thereby performing a write operation of the 3D memory cell array, simultaneously performing a read operation of each memory cell in a first layer of the 3D memory cell array, determining that each memory cell in the first layer has not failed in response to the read operation, and not replacing at least one failed memory cell in the first layer with a first spare memory cell. The simultaneously performing the read operation of each memory cell in the first layer includes comparing a first total read current of each memory cell in the first layer with a first expected read current of each memory cell in the first layer.