3D Semiconductor Memory Structure for Shorter Interconnect Wiring
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Solution Overview
Problem
The scaling of memory technology has slowed, leading to stalled increases in memory capacity and performance, with wires dominating performance and functionality in ICs, and current methods face high energy costs and long latency during memory fetches.
Innovation Solution
A 3D semiconductor device with monocrystalline channels is constructed using alternative methods to ion cut and successive layer transfers, incorporating single crystal transistors, oxide to oxide bonds, and metal to metal bonds, with memory periphery circuits and memory cells in multiple levels, enabling high-speed access and high density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional 2D scaling is continued, then component density increases, but wire performance degrades and energy consumption increases
Solution Approach 1:
The patent transitions from 2D planar scaling to 3D vertical stacking by bonding multiple semiconductor wafers together. This dimensional change allows continued increase in component density while maintaining shorter wire lengths and reducing energy consumption, as components are stacked vertically rather than spread out horizontally with increasingly long interconnect wires.
2Manufacturing precision
If component size is reduced through scaling, then transistor performance improves, but wire degradation increases
Solution Approach 1:
By stacking wafers in the vertical dimension, the patent maintains shorter interconnect wire lengths even as transistor sizes are reduced in the horizontal plane. This preserves wire reliability and signal integrity while still achieving improved transistor performance through continued miniaturization.
3Length of moving object
If 3D stacking is implemented, then wire lengths are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by pre-processing and pre-bonding multiple wafers separately before final assembly. This includes forming through-wafer vias, depositing interconnect layers, and bonding wafers to carriers in advance, which simplifies the overall manufacturing process despite the increased complexity of 3D stacking.
Solution Approach 2:
The manufacturing process is segmented into discrete steps for each wafer layer, allowing independent processing and optimization of each layer before assembly. This modular approach to manufacturing reduces overall complexity by breaking down the complex 3D stacking process into manageable, repeatable units.
4Quantity of substance
If memory capacity is increased through scaling, then storage density improves, but access energy cost increases
Solution Approach 1:
The patent achieves increased memory capacity by stacking memory arrays vertically across multiple wafers rather than expanding horizontally. This 3D arrangement increases storage density while keeping bit-line and word-line lengths relatively short, thereby reducing the energy required for memory access operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces wire lengths, maintains low wiring delay, and enhances integration of logic and memory, providing increased capacity and performance while lowering production costs.
Implementation Method 1
the bonded second level includes oxide to oxide bonds
Implementation Method 2
the bonded second level includes metal to metal bonds
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including first single crystal transistors; a second level including second transistors; memory periphery circuits; and memory cells, where the first level is overlaid by the second level, where the first level includes a transferred layer and a bonded layer, where the second level is bonded to the first level, where the bonded second level includes oxide to oxide bonds, where the bonded second level includes metal to metal bonds, where the first level includes a preponderance of the memory periphery circuits, where the second level includes a preponderance of the memory cells, where the preponderance of the memory periphery circuits are connected to the preponderance of the memory cells using a portion of the metal to metal bonds, and where the memory periphery circuits include at least one Look up Table (“LUT”) circuit.