Multi-Plane Flash Memory Read-Program Parallelism

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Solution Overview

Problem

Conventional multi-plane flash memories face inefficiencies in data processing due to the inability to operate non-selected planes simultaneously, requiring sequential input of commands and data for each plane, which slows down operations and complicates processing.

Innovation Solution

A memory device with a control circuit that allows simultaneous control of read and program operations across multiple planes using a single command, employing data holding circuits to transfer data between planes without external output.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of blocks is increased to increase storage capacity, then storage capacity is improved, but the load capacity of main bit lines increases and reading speed decreases

Engineering Contradiction:

Improvestorage capacityVSAvoidreading speed

Core Design Contradiction:

Quantity of substanceVSSpeed

Solution Approach 1:

The memory cell array is divided into multiple planes (first plane, second plane, etc.), each plane containing multiple blocks. This segmentation allows the system to increase total storage capacity across all planes while maintaining manageable block sizes within each plane, thus preserving reading speed. The controller can selectively activate only the required plane, preventing excessive load on bit lines.

Inventive Principle:

Principle #1Segmentation

2Speed

If sequential reading method is used in multi-plane flash memory, then reading speed is improved, but processing efficiency decreases due to inability to operate non-selected planes simultaneously

Engineering Contradiction:

Improvereading speedVSAvoidprocessing efficiency

Core Design Contradiction:

SpeedVSProductivity

Solution Approach 1:

The patent enables continuous useful action by allowing the controller to simultaneously perform read operations on one plane while preparing or executing operations on other planes. The data holding circuits maintain data from non-selected planes in a ready state, eliminating idle time and enabling continuous processing without sequential waiting, thus improving overall productivity.

Inventive Principle:

Principle #20Continuity of useful action

3Productivity

If data transmission across planes is implemented, then data processing efficiency is improved, but device complexity increases

Engineering Contradiction:

Improvedata processing efficiencyVSAvoiddevice complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

Data holding circuits serve as intermediaries between different planes and the controller. These circuits buffer and temporarily store data from non-selected planes, facilitating efficient data transmission and processing across planes without requiring direct complex inter-plane connections. This intermediary approach simplifies the overall system architecture while enabling cross-plane data operations.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12633352B2Memory device capable of operating multiple planes simultaneously

Publication Date: 2026.05.19 WINBOND ELECTRONICS CORP

AI summary

Disclosed is a flash memory, which includes: a memory cell array including two planes; a controller configured to control the read action and program action of the two planes; and two latches configured to hold data read from one plane or data that should be programmed to one plane; and two latches configured to hold data read from another plane or data that should be programmed to another plane. The controller is configured to perform read operation of the other plane according to a simultaneous command input from the outside while performing programming operation of one plane.