Oxide-Semiconductor Memory Cell Structure With Catalytic Crystallization
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high reliability, large storage capacity, small area occupation, high speed operation, and low manufacturing cost, particularly in three-dimensional memory devices with polycrystalline silicon that has numerous grain boundaries leading to performance variations.
Innovation Solution
Incorporating a semiconductor device with a first semiconductor containing an oxide semiconductor and a second semiconductor with silicon, utilizing a catalytic element like nickel to improve crystallinity, and employing a concentric structure with insulators and conductors to enhance performance and reduce grain boundaries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polycrystalline silicon is used for the semiconductor layer, then manufacturing is easier and cost is lower, but grain boundaries increase making it difficult to improve operation speed and reduce performance variations
Solution Approach 1:
The patent changes the crystalline state parameter of the semiconductor layer from polycrystalline to single crystal through crystallization treatment. This parameter change eliminates grain boundaries while maintaining manufacturing feasibility, thereby improving operation speed and reducing performance variations between memory cells
Solution Approach 2:
The patent introduces a catalytic element as an intermediary substance to facilitate crystallization. The catalytic element promotes the transformation from polycrystalline to single crystal structure, enabling the resolution of grain boundary issues while maintaining processability
2Quantity of substance
If a three-dimensional stacked structure is used, then storage capacity per unit area increases, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional stacked memory cells, utilizing the vertical dimension to increase storage capacity. Multiple memory cells are stacked in the vertical direction, achieving higher density without expanding the chip area
Solution Approach 2:
The patent divides the three-dimensional structure into repeating modular units of memory cells. Each memory cell is segmented with standardized components (semiconductor layer, insulating layers, electrode patterns) that can be stacked and interconnected systematically, managing complexity through modularity
3Reliability
If crystallization treatment is applied to reduce grain boundaries, then operation speed improves, but manufacturing process complexity increases
Solution Approach 1:
The patent introduces a catalytic element as an intermediary to enable crystallization at lower temperatures and with simpler processes. The catalytic element mediates the phase transformation, making the crystallization process more controllable and manufacturable
Solution Approach 2:
The patent incorporates the catalytic element into the semiconductor layer before crystallization treatment. This preliminary action prepares the material structure in advance, facilitating easier and more efficient crystallization during subsequent manufacturing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a highly reliable memory device with increased storage capacity, reduced area occupation, high-speed operation, and lower manufacturing costs, while stabilizing transistor characteristics and reducing variations.
Implementation Method 1
a crystallization technique in which crystalline silicon is formed by using nickel (Ni) or the like as a catalytic element
Implementation Method 2
crystalline silicon is formed by using nickel (Ni) or the like as a catalytic element, for the purposes such as reducing grain boundaries and increasing the crystal size
Data Source
AI summary
A novel semiconductor device is provided. The semiconductor device includes an oxide semiconductor as a first semiconductor, silicon as a second semiconductor, and a plurality of memory cells lined up in a first direction; and a memory cell includes a writing transistor and a reading transistor. The first semiconductor and the second semiconductor extend in the first direction, part of the first semiconductor functions as a channel formation region of the writing transistor, and part of the second semiconductor functions as a channel formation region of the reading transistor. The second semiconductor includes a region in contact with a first layer containing a first metal element.