Variable-Impedance Memory Read Circuit Using Time-to-Transition Sensing
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Solution Overview
Problem
Existing memory technologies, such as DRAM, struggle to efficiently store multiple bits in a single memory cell and perform mathematical operations due to limitations in voltage change detection during read operations.
Innovation Solution
Implementing memory devices with variable impedance memory cells that utilize a read circuit to measure the time delay of a signal node voltage change, allowing for time-to-transition sensing to determine the data value stored, thereby enabling multiple bits to be stored and facilitating mathematical operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If variable impedance memory cells are used to store multiple bits in a single cell, then storage capacity is improved, but reading accuracy deteriorates due to difficulty in determining data values based on impedance variations
Solution Approach 1:
The patent transforms the impedance-based storage mechanism into a time-based readout mechanism. By converting the physical parameter from impedance (electrical property) to time (temporal property), the system can accurately distinguish multiple stored bits through time-to-transition measurements, resolving the accuracy problem while maintaining high storage capacity
Solution Approach 2:
The patent replaces the traditional electrical measurement system (impedance measurement) with a temporal measurement system (time delay determination). This substitution allows for more precise discrimination of multiple stored values by measuring the time it takes for voltage transitions to occur, rather than attempting to directly measure impedance variations
2Productivity
If traditional reading methods are used for variable impedance memory cells, then device complexity is reduced, but data retrieval speed deteriorates
Solution Approach 1:
The patent introduces dynamic time-based measurement instead of static impedance measurement. The read circuit dynamically measures the time-to-transition of voltage changes, which naturally adapts to different stored values without requiring complex switching or multiplexing circuits, thus improving speed while keeping the circuit relatively simple
Solution Approach 2:
The patent employs periodic voltage transitions and time-based sampling to read multiple bits from a single memory cell. By using periodic action in the time domain, the system can extract multiple bits of information through sequential time measurements, increasing data retrieval speed without proportionally increasing circuit complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances data storage capacity and computational efficiency by accurately determining data values based on the time taken for bit lines to discharge to a threshold, supporting advanced computing applications.
Implementation Method 1
each memory cell having a variable impedance that varies in accordance with a respective data value stored therein
Implementation Method 2
a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change
Data Source
AI summary
The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a memory array including a plurality of memory cells, each memory cell having an impedance that varies in accordance with a respective data value stored therein; and a tracking memory cell having an impedance based on a tracking data value stored therein; and a read circuit coupled to the memory array, the read circuit configured to determine an impedance of a selected memory cells with respect to the impedance of the tracking memory cell; read a data value stored within the selected memory cell based upon a voltage change of a signal node voltage corresponding to the impedance of the selected memory cell.