Memory Block Scan Layout for Concurrent Reads Without Data Overlap
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Solution Overview
Problem
Memory devices with reduced planes for increased storage capacity face limitations in concurrent read operations due to shared sense amplifiers, leading to increased read latency and decreased performance, especially during scan operations to check data reliability.
Innovation Solution
Implementing a dummy word line with staggered programming of transistors in memory blocks, allowing each sub-block to be coupled with a separate sense amplifier, enabling concurrent scanning of multiple blocks without overlapping data on the amplifiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scan operations are performed sequentially on each block using shared sense amplifiers, then hardware complexity is reduced, but scan time increases and productivity decreases
Solution Approach 1:
The memory array is divided into multiple independent blocks, each with its own dedicated sense amplifiers. This segmentation allows parallel scan operations on multiple blocks simultaneously, reducing total scan time from sequential processing to concurrent processing, directly resolving the productivity versus complexity contradiction
Solution Approach 2:
Each block's sense amplifiers are designed to serve multiple functions: they can perform both normal read operations and scan operations within the same block. This multi-functionality allows the dedicated sense amplifiers to be utilized efficiently for both data retrieval and error detection purposes, justifying the increased hardware complexity
2Productivity
If multiple blocks are scanned concurrently using shared sense amplifiers, then scan time is reduced, but data overlap occurs and measurement precision deteriorates
Solution Approach 1:
By allocating dedicated sense amplifiers to each block, the system segments the data path so that scan data from different blocks does not overlap or interfere with each other. Each sense amplifier processes data from its assigned block independently, ensuring measurement precision while enabling concurrent scan operations across multiple blocks
Solution Approach 2:
The dummy word line acts as an intermediary control mechanism that selectively activates transistors in memory cells during scan operations. This intermediary structure enables precise control over which cells are accessed, preventing data overlap between concurrent operations while maintaining high scan operation speed
3Manufacturing precision
If the number of planes is reduced to increase block size, then manufacturing precision is improved, but concurrent read operations are limited and productivity decreases
Solution Approach 1:
Each block is further segmented into multiple sub-blocks, each with dedicated sense amplifiers. This hierarchical segmentation allows concurrent read operations within a block by accessing different sub-blocks simultaneously, maintaining productivity even when the total number of planes is reduced and block size is increased
Solution Approach 2:
The patent introduces a sub-block dimension within each block, creating a two-level hierarchy (blocks containing sub-blocks). This dimensional organization enables parallel access paths within blocks, compensating for the reduced number of planes and maintaining concurrent read operation capability while allowing larger block sizes for improved manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces scan operation time, decreases read latency, and improves memory device performance by allowing faster execution of read commands while maintaining data reliability.
Implementation Method 1
a first transistor of the set of transistors coupled to the dummy word line of each block is programmed to a low threshold voltage, and a second transistor of the set of transistors coupled to the dummy word line of each block is programmed to a high threshold voltage
Data Source
AI summary
Control logic in a memory device selects two or more blocks of a plurality of blocks to concurrently scan during a scan operation. The control logic can further cause a first voltage to be applied to a dummy word line of each block of the two or more blocks to selectively couple a string of memory cells in each block of the two or more blocks to a different sense amplifier of a set of sense amplifiers coupled with the plurality of blocks. The control logic can cause a second voltage to be applied to a selected word line of each block of the two or more blocks to read a bit stored at a respective memory cell of the string of memory cells in each block out to the set of sense amplifier.