Anti-Fuse OTP Memory Cell Structure for Secure State Stability
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Solution Overview
Problem
Existing anti-fuse OTP memory devices are not entirely satisfactory in all respects, particularly in terms of their security and reliability in secure key storage and code storage applications.
Innovation Solution
The OTP memory device incorporates a memory array with N-type and P-type memory cells, each having channel layers and gate structures, and a wall structure that enhances the integration and reliability of the anti-fuse gate structure, allowing for secure programming and reading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If anti-fuse OTP memory cells are programmed once, then the storage state is determined and cannot be modified, but this limitation reduces the adaptability for security applications
Solution Approach 1:
The memory array is segmented into multiple memory cells with different types (N-type and P-type) that have distinct programming characteristics. This allows different cells to serve different security functions - some programmed once for stable storage, others programmable multiple times for flexibility, resolving the contradiction between reliability and adaptability
Solution Approach 2:
Different regions of the memory array have different programming properties. N-type memory cells provide one-time programming with high reliability for secure storage, while P-type memory cells provide re-programmability for flexibility. Each region is optimized for its specific security application requirement
2Object-affected harmful factors
If OTP memory cells are designed for secure key storage, then security is improved, but the device complexity increases due to multiple memory cell types and gate structures
Solution Approach 1:
The patent combines N-type and P-type memory cells in a unified memory array with shared word-line gate structures. This merging approach maintains security through diverse cell types while reducing complexity by sharing common infrastructure, achieving both security improvement and complexity control
Solution Approach 2:
The word-line gate structures serve multiple functions: programming N-type cells, programming P-type cells, and reading from both types. This multi-functionality reduces the need for separate dedicated structures, thereby controlling device complexity while maintaining security
Data Source
AI summary
A one-time-programmable (OTP) memory device includes a memory array including an N-type memory cell and a P-type memory cell. The N-type memory cell includes first channel layers and second channel layers. The P-type memory cell includes third channel layers and fourth channel layers. The N-type memory cell and the P-type memory cell further include a first word-line gate structure extending in the Y-direction and wrapping around the first channel layers and the third channel layers, and an anti-fuse gate structure extending in the Y-direction and wrapping around the second channel layers and the fourth channel layers. The OTP memory device further includes a wall structure extending in an X-direction and between the N-type memory cell and the P-type memory cell in the Y-direction. The first channel layers, the second channel layers, the third channel layers, and the fourth channel layers attach on the wall structure.