3D NAND Staircase Layout for Reduced RC Delay

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Solution Overview

Problem

As 3D NAND devices migrate towards higher density and capacity, reduced layer dimensions lead to increased sheet resistance, causing resistance-capacitance (RC) delay in drive currents across memory planes.

Innovation Solution

A novel structure is introduced in 3D NAND devices with a stair area positioned in the middle of the plane, featuring alternating staircases coupled to decode structures, reducing the flow length of drive currents to half the plane length, thereby compensating for increased sheet resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If layer dimensions are reduced to increase density, then storage capacity is improved, but sheet resistance increases causing RC delays

Engineering Contradiction:

Improvestorage capacityVSAvoidRC delay

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The memory plane is divided into multiple segments, each served by its own decode structure positioned at different locations within the plane. This segmentation allows drive currents to travel shorter distances within each segment, reducing the overall RC delay while maintaining high storage capacity through the divided architecture

Inventive Principle:

Principle #1Segmentation

2Device complexity

If decode structures are positioned at plane boundaries, then device complexity is reduced, but drive current flow length increases causing RC delays

Engineering Contradiction:

Improvedecode structure arrangementVSAvoidRC delay

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

Decode structures are positioned at multiple locations within the plane rather than only at boundaries, utilizing the two-dimensional space more effectively. This dimensional redistribution of decode structures creates multiple access points, reducing current flow paths without significantly increasing overall device complexity

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12615773B2Three-dimensional NAND memory device with reduced resistance-capacitance delay

Publication Date: 2026.04.28 YANGTZE MEMORY TECH CO LTD

AI summary

A semiconductor device is provided that can include a stack formed of word line layers and insulating layers that are alternatingly stacked over a substrate. A first staircase of a first block can be formed in the stack and extend between first array regions of the first block. A second staircase of a second block can be formed in the stack and extend between second array regions of the second block. The semiconductor device further can have a connection region that is formed in the stack between the first staircase and second staircase.