Dummy Word Line Voltage Biasing for 3D Memory Program Disturbance

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Solution Overview

Problem

Program disturbance in three-dimensional memory structures leads to higher failure rates as the number of layers increases, necessitating a solution to reduce this issue.

Innovation Solution

Adjusting the bias and threshold voltages of dummy word lines in the upper and lower decks of a three-dimensional memory to manage differences between these voltages within specific thresholds to mitigate program disturbance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of layers in a three-dimensional memory structure is increased to increase capacity, then the storage capacity is improved, but the program disturbance becomes more serious leading to higher failure rates

Engineering Contradiction:
Improvestorage capacityVSAvoidprogram disturbance
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent applies parameter changes by adjusting the voltage levels applied to dummy word lines during programming operations. Specifically, different voltage levels are used for dummy word lines in different decks (upper vs. lower) to control and reduce program disturbance. This voltage parameter adjustment allows the memory to maintain high storage capacity while mitigating the increased program disturbance that would otherwise result from the multi-layer structure.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the number of layers is increased to store more data on the same area, then the memory capacity is improved, but the program disturbance leads to higher failure rate of programming

Engineering Contradiction:
Improvedata storage densityVSAvoidprogramming failure rate
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements local quality by applying different voltage levels to dummy word lines in different local regions (decks) of the memory structure. The upper deck dummy word lines receive different voltage levels compared to lower deck dummy word lines, allowing localized control of program disturbance in each deck region while maintaining high overall storage density.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12633356B2Method and memory used for reducing program disturbance by adjusting voltage of dummy word line
Publication Date: 2026.05.19 YANGTZE MEMORY TECH CO LTD
  • US12633356B2 patent drawing
  • US12633356B2 patent drawing
  • US12633356B2 patent drawing

AI summary

A method for operating a memory device is provided. The memory device includes a first word line, a second word line, a first dummy word line, and a second dummy word line. The first dummy word line and the second dummy word line are between the first word line and the second word line. A first pass voltage is applied to the first dummy word line in a program operation. A second pass voltage is applied to the second dummy word line in the program operation. The first pass voltage is different from the second pass voltage.