3D NAND Read Voltage Grouping for Interlayer Interference
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Solution Overview
Problem
The reliability of 3D NAND flash memory is hindered by interlayer interference between adjacent word lines, leading to increased bit error rates and reduced reliability due to widened threshold voltage distributions during multi-level cell programming.
Innovation Solution
A memory system and method that groups memory cells based on voltage differences after two-stage programming, dividing them into groups with different interlayer interference levels, and applies specific read voltages based on these groups to improve reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacking layers is increased to enhance storage capacity, then the storage capacity is improved, but the interlayer interference between adjacent word lines increases leading to widened threshold voltage distributions and reduced reliability
Solution Approach 1:
The patent segments memory cells into different groups (first group and second group) based on their programming states and voltage characteristics. By applying different read voltages to different groups, the system reduces interlayer interference effects and narrows threshold voltage distributions, thereby maintaining reliability while preserving increased storage capacity from multiple stacking layers.
Solution Approach 2:
The patent applies different read voltages to different groups of memory cells based on their specific programming states and interference characteristics. This localized approach allows optimal reading conditions for each group, compensating for varying interlayer interference effects across different memory cell groups and improving overall system reliability.
2Manufacturing precision
If two-stage programming is applied to memory cells, then programming consistency is improved, but the complexity of the programming operation increases
Solution Approach 1:
The programming process is segmented into two distinct stages with different voltage applications. The first stage programs memory cells to initial states, and the second stage refines the programming based on verification results. This segmentation improves programming consistency by allowing controlled adjustment of voltage parameters at each stage, with the added benefit that different read voltages can be applied to different groups afterward.
3Measurement precision
If different read voltages are applied to different groups of memory cells, then read accuracy is improved, but the complexity of the read operation increases
Solution Approach 1:
Memory cells are segmented into different groups based on their programming states and interlayer interference characteristics. Each group receives appropriately optimized read voltages to maximize signal detection accuracy. This segmentation enables improved read accuracy for cells experiencing different interference levels while maintaining manageable operational complexity through systematic voltage application.
Solution Approach 2:
Different read voltages are applied locally to different groups of memory cells based on their specific characteristics and interference exposure. This localized optimization improves read accuracy for each group while the overall system manages complexity through organized voltage distribution patterns.
Data Source
AI summary
A memory includes a memory array and a peripheral circuit, wherein the memory array includes memory cells; the memory cells include a plurality of first memory cells coupled with a first selected word line, and a plurality of second memory cells coupled with a second selected word line; and the peripheral circuit is configured to: acquire a grouping result of the plurality of second memory cells, and if a first memory cell is coupled with a second memory cell in a first group through a first bit line, apply a first read voltage to the first memory cell at a first read duration; and if a first memory cell is coupled with a second memory cell in a second group through a second bit line, apply a second read voltage to the first memory cell at a second read duration.