Memory String Voltage Sequencing for Write-Stop Threshold Control
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently managing write operations, particularly in ensuring accurate data storage and retrieval due to variations in threshold voltages and potential errors during transitions between write and read states.
Innovation Solution
The semiconductor memory device employs a specific timing sequence for voltage changes across gate electrodes and drain electrodes of memory and selection transistors, including controlled rises and falls of voltages at precise timings to manage write operations effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If voltage timing is not precisely controlled during write operations, then write operation speed is improved, but defects in selection transistors occur and threshold voltage varies
Solution Approach 1:
The patent applies preliminary action by setting the bit line voltage to a predetermined level before the write operation begins. This pre-conditioning of the bit line voltage ensures that when the write operation starts, the voltage timing relationships are already optimized, preventing selection transistor defects while maintaining high write speed. The bit line voltage is prepared in advance at a specific level that will be effective during the actual write pulse application.
2Ease of operation
If voltage timing is not precisely controlled during write operations, then write operation simplicity is improved, but threshold voltage accuracy deteriorates
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting multiple voltage parameters during the write operation sequence. Specifically, the bit line voltage is changed to a predetermined level before writing, the selected word line voltage is raised during the write pulse, and other line voltages are coordinatedly adjusted. These parameter changes ensure accurate threshold voltage programming while maintaining operational simplicity through automated voltage sequencing.
3Productivity
If voltage timing is not precisely controlled during write operations, then write operation efficiency is improved, but read operation accuracy deteriorates
Solution Approach 1:
The patent applies feedback by implementing a coordinated voltage timing sequence where subsequent voltage adjustments are based on the completion of previous voltage transitions. The bit line voltage is set to a predetermined level, then the word line voltage is raised, and other line voltages are adjusted in response to these changes. This feedback-based voltage sequencing ensures that write operations complete efficiently while leaving memory cells in a stable state that enables accurate subsequent read operations.
Data Source
AI summary
In a semiconductor memory device, in a write operation performed to a memory cell transistor, a first voltage is applied to a first word line and a second voltage lower than the first voltage is applied to a second word line. When a stop command is received during the write operation, a third voltage lower than the second voltage is applied to the first and second word lines, thereafter a fourth voltage higher than the third voltage is applied to a first selection line, thereon or thereafter a fifth voltage higher than the fourth voltage is applied to the first and second word lines, thereafter a sixth voltage lower than the fourth voltage is applied to the first selection line, and thereafter a seventh voltage is applied to the first and second word lines.