Antifuse Memory Cell Layout to Prevent Silicide Spike Disturbance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing antifuse-type non-volatile memory cells face issues with program disturbance due to the formation of silicide spike material during the programming process, leading to leakage currents and program failure, especially in CMOS semiconductor manufacturing processes.
Innovation Solution
The proposed antifuse-type non-volatile memory cell incorporates protecting layers to cover the n-doped regions, preventing the formation of silicide spike material and reducing program disturbance by ensuring that electrical contact layers are not formed on these regions, thus maintaining the integrity of the memory cell during programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electrical contact layers are formed on n-doped regions during the silicide formation process, then low contact resistance is achieved, but silicide spike material forms causing program disturbance
Solution Approach 1:
The patent applies preliminary action by forming a protecting layer on the n-doped regions before the electrical contact layer formation process. This protecting layer prevents silicide spike material formation during subsequent heating processes, eliminating program disturbance while allowing low-resistance contact to be established in controlled areas only.
Solution Approach 2:
The patent implements local quality by selectively applying the protecting layer only to specific n-doped regions where silicide spike formation would cause harm. This allows electrical contact layers to be formed on other regions with low contact resistance, achieving local optimization rather than global restriction.
2Reliability
If protecting layers are introduced to prevent silicide spike formation, then program disturbance is reduced, but device structure and manufacturing process become more complex
Solution Approach 1:
The protecting layer is formed as a preliminary step in the manufacturing process, before electrical contact layers are deposited. This preliminary action prevents harmful silicide spike formation without requiring complex modifications to subsequent processing steps, integrating smoothly into the existing CMOS fabrication flow.
Solution Approach 2:
The protecting layer serves as an intermediary element between the n-doped region and the electrical contact layer. It mediates the interaction during heating processes, preventing direct formation of silicide spikes while allowing the electrical contact layer to maintain its low-resistance function in areas where the protecting layer is removed or absent.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces program disturbance and ensures reliable programming by preventing the formation of silicide spikes, thereby enhancing the reliability and performance of the antifuse-type non-volatile memory cells.
Implementation Method 1
a silicide formation process in the CMOS semiconductor manufacturing process... the contact regions between the metal film 130 and the silicon material are reacted and formed as silicide layers
Data Source
AI summary
An antifuse-type non-volatile memory cell includes a select transistor, a following transistor and a capacitor. The first drain/source terminal of the select transistor is connected with a bit line. The gate terminal of the select transistor is connected with a word line. A first drain/source terminal of the following transistor is connected with a second drain/source terminal of the select transistor. A gate terminal of the following transistor is connected with a following line. A second drain/source terminal of the following transistor is connected with a first terminal of the capacitor. A second terminal of the capacitor is connected with an antifuse control line.