3D Semiconductor Stack With Power Delivery and Heat-Protected Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current 3D semiconductor chip stacking technologies face challenges in constructing transistors at high temperatures, leading to damaged wiring layers and limited connectivity due to misalignment and high defect densities, which hinder the development of high-density connections between layers.
Innovation Solution
The development of 3D semiconductor devices with single crystal transistors and isolation layers, incorporating a power delivery path and capacitors, and using optical annealing techniques to activate dopants without damaging underlying metal interconnects, allowing for high-density connectivity and efficient heat removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are constructed at high temperatures to improve transistor performance and density, then transistor functionality is improved, but the underlying wiring layers are damaged
Solution Approach 1:
The device is divided into multiple stacked levels (first level with transistors, second level with wiring, third level with additional transistors), allowing high-temperature processing of transistor layers without exposing the wiring layer to damaging temperatures. Each level can be processed independently at appropriate temperatures.
Solution Approach 2:
A heat spreader layer is introduced between the high-temperature transistor layer and the temperature-sensitive wiring layer. This intermediary structure absorbs and distributes heat, protecting the wiring layer from thermal damage while allowing transistor formation at elevated temperatures.
2Manufacturing precision
If contact size is increased to improve alignment tolerance between layers, then alignment issues are reduced, but device density decreases
Solution Approach 1:
The patent transitions from 2D planar contacts to 3D vertical through-silicon vias (TSVs) and contact structures. This dimensional change allows for smaller contact footprints while maintaining alignment tolerance through the vertical stacking approach, thereby preserving device density.
Solution Approach 2:
Multiple contact structures are nested within the vertical stack, with contacts at different levels interconnected through vias. This nesting allows for complex interconnections with minimal lateral space, maintaining high density while providing multiple alignment reference points.
3Adaptability or versatility
If the number of contacts between layers is increased to improve connectivity, then inter-layer communication is improved, but manufacturing complexity increases
Solution Approach 1:
The through-silicon via structures serve multiple functions simultaneously: they provide electrical connectivity between layers, act as alignment references, and function as part of the power delivery network. This multi-functionality reduces the need for separate specialized structures, simplifying manufacturing.
Solution Approach 2:
The patent combines power delivery paths with signal interconnect structures, and merges contact formation with via formation processes. By consolidating multiple functions into unified structures and process steps, manufacturing complexity is reduced while maintaining high connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the construction of 3D semiconductor chips with improved connectivity and reduced thermal resistance, maintaining transistor performance and reliability while overcoming temperature limitations.
Implementation Method 1
incorporating heat spreading materials to manage thermal resistance and protect sensitive metal interconnects during high-temperature processing
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, and where the third level is bonded to the second level; a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors; and a plurality of capacitors, where the single crystal first transistors or the second transistors include at least two FinFet transistors, and where two of the at least two FinFet transistors have different threshold voltages (Vt).