3D Flash Memory Floating Devices for Vertical Scaling
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Solution Overview
Problem
Existing 3D flash memory structures with floating devices face challenges in vertical scaling due to the need for blocking oxide and polycrystalline silicon within a flattened 'C'-shaped structure, making it difficult to achieve multi-level implementation and reliability.
Innovation Solution
A manufacturing method for 3D flash memory involving the formation of a simplified structure with floating devices, including the removal of interlayer insulating layers to create air gaps and using a thermal oxidation process to form isolated floating devices, allowing for vertical scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If blocking oxide and polycrystalline silicon are provided within a flattened 'C'-shaped structure, then floating devices can be included in the 3D flash memory, but vertical scaling becomes very difficult to implement
Solution Approach 1:
The patent segments the floating device layer into multiple isolated floating devices by removing portions of the interlayer insulating layers between them. This creates discrete, independently controllable floating devices while maintaining the overall 3D structure, resolving the contradiction between including floating devices and enabling vertical scaling.
Solution Approach 2:
The patent extracts and removes specific interlayer insulating layers from between the floating device layer and the charge storage film, creating air gaps or voids that isolate individual floating devices. This extraction approach enables vertical scaling by creating a simplified structure that can be stacked without the complexity of the flattened 'C'-shaped configuration.
2Productivity
If a conventional 3D flash memory structure is used with alternately stacked word lines and interlayer insulating layers, then the basic memory array can be formed, but the structure becomes complex and difficult to scale vertically
Solution Approach 1:
The patent removes selected interlayer insulating layers from the alternately stacked structure to create air gaps that isolate floating devices. This extraction simplifies the overall structure by eliminating unnecessary insulating layers while preserving the memory array functionality, thereby enabling vertical scaling.
Solution Approach 2:
The patent discards (removes) specific interlayer insulating layers that are no longer needed for electrical isolation in the modified structure. By removing these layers and creating air gaps instead, the patent recovers manufacturing simplicity and enables vertical scaling while maintaining the essential memory array formation capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables a simplified 3D flash memory structure that facilitates vertical scaling while maintaining the functionality of floating devices, enhancing multi-level implementation and reliability.
Implementation Method 1
a charge storage layer formed to surround the channel layer
Implementation Method 2
removing regions corresponding to the plurality of interlayer insulating layers in the floating device layer to form a plurality of floating devices isolated from each other
Data Source
AI summary
A three-dimensional flash memory including floating devices and a manufacturing method therefor are disclosed. A method for manufacturing a three-dimensional flash memory according to an embodiment may comprise the steps of: preparing a semiconductor structure including a plurality of word lines and a plurality of interlayer insulating layers, which are alternately stacked in a vertical direction while extending in a horizontal direction, respectively, and at least one memory cell string formed extending through the plurality of word lines and the plurality of interlayer insulating layers in the vertical direction, wherein the at least one memory cell string constitutes a plurality of memory cells corresponding to the plurality of word lines, while including a channel layer formed extending in the vertical direction, a charge storage layer formed to surround the channel layer, and a floating device layer formed extending to surround the charge storage layer; removing the plurality of interlayer insulating layers from the semiconductor structure; and removing regions of the floating device layer corresponding to the plurality of interlayer insulating layers, in order to form a plurality of floating devices isolated from each other.