3D Flash Memory Erase Method Using Floating Bit Lines
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Solution Overview
Problem
The increasing number of stacked word lines in three-dimensional flash memory devices leads to increased chip thickness, making it difficult to perform bulk erase operations, which is technically impractical due to semiconductor package requirements.
Innovation Solution
A memory device and method that perform an erase operation by applying an erase voltage to one bit line while keeping another bit line in a floating state, allowing for effective erase operations without increasing chip thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked word lines is increased to increase integration density, then integration density is improved, but chip thickness increases making bulk erase operations impossible
Solution Approach 1:
The invention divides the erase operation into two independent phases: a first erase operation on a first cell string and a second erase operation on a second cell string. This segmentation allows each operation to be performed independently with optimized voltage conditions, enabling effective erase operations in thinned three-dimensional flash memory without requiring bulk erase methods.
Solution Approach 2:
The invention dynamically switches between different voltage conditions for different bit lines during the erase operation. Specifically, it applies an erase voltage to a first bit line while placing a second bit line in a floating state, and vice versa for subsequent operations. This dynamic voltage switching enables effective erase operations in thinned memory structures where bulk erase is not feasible.
2Ease of operation
If bulk erase method is used to erase memory cells, then erase operation is simple, but it becomes difficult to perform when chip thickness is reduced
Solution Approach 1:
The bulk erase operation is segmented into multiple independent erase operations performed on different cell strings sequentially. Each erase operation targets specific cell strings connected to different bit lines, allowing the system to achieve complete erasure without relying on bulk erase methods that require thick chip structures.
Solution Approach 2:
The invention employs dynamic voltage switching between different bit lines during the erase sequence. By applying erase voltage to one bit line while floating another, then switching roles in subsequent operations, the system maintains ease of operation through controlled voltage transitions while adapting to thinned chip structures where bulk erase is impossible.
3Productivity
If erase voltage is applied to both bit lines simultaneously, then erase operation is efficient, but it causes interference between adjacent cell strings in thinned structures
Solution Approach 1:
The simultaneous erase operation is segmented into sequential operations on different cell strings. By erasing one cell string at a time through controlled voltage application to specific bit lines while floating others, the invention eliminates interference between adjacent cell strings that would occur in thinned structures, while still achieving efficient complete erasure through the segmented approach.
Solution Approach 2:
The invention dynamically controls voltage application to different bit lines in a time-sequential manner. During the first erase operation, voltage is applied to the first bit line while the second bit line is floating; during the second erase operation, voltage is applied to the second bit line while the first bit line is floating. This dynamic switching prevents interference between cell strings in thinned structures while maintaining erase efficiency.
Data Source
AI summary
A memory device includes a cell array and a page buffer circuit. The cell array includes first and second cell strings respectively connected to first and second bit lines. The page buffer circuit is configured to apply an erase voltage to the first bit line and to allow the second bit line to be in a floating state, when an erase operation is performed on memory cells of the first and second cell strings.