Read-Only Memories TRIZ Cases

Dual bit storage in a 1T ROM cell merges channel and diffusion regions to increase density without reducing device width or reliability.

Integrating deck select transistors within word line structures of a three-dimensional cross-point memory array.

Parallel PMOS and NMOS sub-blocks manage voltage selection in phase change memory column decoders, eliminating high-voltage transistors.

Aligns configuration array wordlines and bitlines with data arrays to standardize manufacturing layouts, reducing defects from mismatched orientations.

A dynamic random access memory cell uses capacitor breakdown to enable one-time programming without electronic fuses.

A nonvolatile memory erase method segments operations into multiple loops with distinct voltage increments to narrow threshold voltage distributions.

Dynamic body effect adjustment in sense amplifier data latches reduces energy per bit during memory read operations.

Address re-mapping replaces defective memory sub-blocks within grouped regions, maintaining electrical characteristics despite high integration density.

Simultaneously adjusts MSB and LSB read voltages by analyzing threshold voltage distributions across paired pages, reducing read errors in MLC devices.

A non-volatile memory system loads operating parameters into data latches before transferring them to registers for read and write operations.

A semiconductor memory device transitions cells between volatile and nonvolatile states using signal line drivers to adjust voltage and current levels.

A soft decoding method uses hard read data to determine reference data when initial decoding fails.

Processing units embedded in non-volatile memory manipulate data in-place to bypass the Von Neumann bottleneck and reduce latency.

Memory sub-systems compute optimized read voltages using signal and noise characteristics to enhance data retrieval efficiency.

A data loading circuit uses a deserializer and load controller to store bits in segmented units.

Estimating read threshold offsets allows modifying reliability measures to compensate for positioning errors, reducing latency and power consumption.

A control cell tracks data inversion states in SRAM and non-volatile memory pairs to optimize write speed.

A critical condition detector monitors voltage ratios between logic components and memory cells to inhibit word line signals when operating ranges are exceeded.

Consecutive verification operations in non-volatile memory reduce programming latency by overlapping data latch usage and sensing phases.

Segmented coarse and fine programming pulses mitigate program disturb while improving speed.

A DRAM voltage system uses a control device to enable only required regulators based on operation modes.

A nonvolatile memory device uses overlapping pulse signals to program grouped cells sequentially.

A non-volatile memory process narrows erased threshold voltage distributions by applying targeted programming pulses to over-erased bit lines.

A memory controller detects interrupted programming states in one-time programmable memory to resume operations from the exact interruption point.

Lowering voltage on non-selected word lines reduces read disturb and bit error rates when detecting the last written page in partially written NAND blocks.

Dynamic current adjustment boosts flash memory writing speed while suppressing noise from charge pump load.

A control module monitors non-volatile memory temperature to adapt refresh cycles dynamically.

Dynamic pulse width regulation reduces electrical stress on electrical fuses, increasing cumulative read access cycles from 2 million to 200 million.

Dynamic pass voltage adjustment widens the programming window, resolving narrow voltage margins that delay development and reduce reliability.

A memory controller adjusts program verify voltage levels based on host request patterns to optimize operation speeds.

Valley detection analyzes cumulative occurrence counts to resolve threshold voltage shifts and maintain read accuracy.

Antifuse memory cell reduces programming power by using soft breakdown in thin gate oxide and local sense transistor to amplify signal for low voltage read.

A memory controller monitor circuit digitizes manufacturing variation signals to detect characteristic changes.

Alternating active address counters between dual memory banks reduces power consumption during data output while maintaining high-speed transfer.

A controller pre-charges specific bit lines to reduce read errors in non-volatile memory arrays.

A page buffer circuit uses a data change unit to alter latch voltage levels for accurate lower and upper page programming.

Segmented erase operations on independent cell strings prevent interference in thinned 3D flash structures where bulk erasure fails.

A floating gate transistor programming method applies a program voltage while concurrently verifying cell current against a threshold to determine completion.

A memory control circuit adjusts write voltage parameters based on operating temperature to optimize data writing operations.

Applying a weak erase voltage generates gate-induced drain leakage holes for in situ re-programming, preventing program disturb in neighboring cells.

Lowering the boost voltage on non-selected main word lines reduces the electric field at PMOS gate oxide films, suppressing Gate Induced Drain Leakage current.

Dynamic hold mode gate voltage adjustment manages floating body carrier density, enhancing sense margin and data retention.

Partial programming equalizes cell voltage levels to prevent forensic recovery, resolving the trade-off between deletion simplicity and data security.

Asymmetric read pass voltages applied to unselected word lines in NAND flash memory.

A data buffer uses coupled amplifiers to invert and output input data signals across varying swing levels.

A semiconductor memory data latch circuit uses parallel N-channel and P-channel MOS transistors to maintain signal integrity between sense amplifiers and I/O buses.

Dynamic program erase targeting adjusts erase distribution voltage based on bit error rate feedback to optimize memory cell programming distributions.

Offset memory component automatic calibration error recovery updates current read level signals to account for threshold voltage shifts, reducing bit errors.

Staged discharge of word and select lines maintains channel voltage in unselected strings, preventing program disturbance during cell programming.

Hybrid read operations erase nonvolatile memory data after access to prevent unauthorized retention and enhance security.