Flash Memory Write Speed and Noise Control

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Solution Overview

Problem

Current methods for writing to flash memory in semiconductor devices do not sufficiently shorten writing time, and as the capacity of flash memory increases, test time and cost also increase, with higher current demand leading to increased noise and load on the charge pump.

Innovation Solution

A semiconductor device configuration that includes a memory controller performing a first write operation with a smaller current for multiple memory cells and a second write operation with a larger current for cells that have not completed writing, using a sense amplifier to determine completion and adjust current values accordingly, thereby improving writing speed while minimizing noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of selected cells at the time of data rewriting is increased, then the throughput is improved and the writing time is shortened, but the load on the charge pump increases because more current is required and the influence of noise due to an increase in the amount of current also increases

Engineering Contradiction:
Improvewriting speedVSAvoidnoise
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The writing operation is divided into two distinct modes: a first writing mode that writes to a first number of memory cells with a first writing current, and a second writing mode that writes to a second number of memory cells with a second writing current. This segmentation allows the system to handle different numbers of cells with appropriate current levels, improving overall writing speed while controlling noise by not applying high current to all cells simultaneously.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The writing current is made dynamic rather than static. The system automatically adjusts the writing current based on the number of selected memory cells: when more cells are selected, it uses the first writing current (lower current), and when fewer cells are selected, it uses the second writing current (higher current). This dynamic adjustment optimizes the balance between writing speed and noise generation.

Inventive Principle:
Principle #15Dynamics

2Productivity

If the number of selected cells at the time of data rewriting is increased, then the throughput is improved and the writing time is shortened, but the load on the charge pump increases because more current is required

Engineering Contradiction:
Improvewriting speedVSAvoidcharge pump load
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The writing operation is segmented into two modes with different current characteristics. The first writing mode handles a larger number of cells with lower current, reducing the peak load on the charge pump. The second writing mode handles fewer cells with higher current when needed. This segmentation prevents the charge pump from being overloaded while maintaining high throughput.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The writing current parameter is changed based on the operating conditions. The system switches between a first writing current value and a second writing current value depending on the number of selected cells. This parameter change allows the charge pump to operate within its capacity limits while achieving high writing speeds when fewer cells are involved.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10896737B2Semiconductor device
Publication Date: 2021.01.19 RENESAS ELECTRONICS CORP
  • US10896737B2 patent drawing
  • US10896737B2 patent drawing
  • US10896737B2 patent drawing

AI summary

An object of the present invention is to increase a writing speed to a flash memory while suppressing an increase in noise. In the high-speed write mode, the memory controller simultaneously performs a first write operation with a second write current having a current value smaller than the first write current with respect to a second number of memory cells having a larger number than the first write current. At the completion of the first write operation, the memory controller simultaneously performs the second write operation by the third write current having a larger current value than the second write current with respect to the memory cell determined by the sense amplifier to have not completed the write operation in the determination process.