Nonvolatile Memory Erase Loop Voltage Increment Segmentation
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Solution Overview
Problem
Flash memory devices face challenges in achieving uniform threshold voltage distribution during the erase process, leading to reduced speed and data retention capacity due to variations in physical positions and characteristics of memory blocks and cells, resulting in a 'deep erase' state with low threshold voltages.
Innovation Solution
A method involving multiple erase loops with different schemes, including post-program operations and adjustments to erase voltage increments based on detected threshold voltage distributions, is employed to improve the erase state of memory blocks in nonvolatile memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an erase voltage is applied to a substrate to erase memory blocks, then the threshold voltages of memory cells are lowered, but the threshold voltage distribution becomes wide due to physical position variations, resulting in deep erase state with low threshold voltages that reduces program speed and data retention
Solution Approach 1:
The erase operation is divided into multiple erase loops with different erase voltage increments. The method segments the erase process into at least a first erase loop and a second erase loop, where each loop uses a different erase voltage increment strategy. This segmentation allows the system to address different portions of the threshold voltage distribution separately, improving overall uniformity while maintaining reliability.
Solution Approach 2:
The method changes the erase voltage increment parameter between different erase loops. In the first erase loop, a first erase voltage increment is used, and in the second erase loop, a second erase voltage increment (different from the first) is used. This parameter change allows optimization of the erase process at different stages, narrowing the threshold voltage distribution without causing deep erase state that would harm data retention.
2Manufacturing precision
If multiple erase loops are performed with different erase voltage increments, then the threshold voltage distribution is narrowed, but the complexity of the erase operation increases
Solution Approach 1:
The method applies different erase voltage increments to different stages of the erase process rather than using a uniform approach throughout. The first erase loop uses a first erase voltage increment while the second erase loop uses a second erase voltage increment, allowing localized optimization at different points in the erase sequence. This local quality approach narrows the threshold voltage distribution without requiring complete redesign of the entire erase system.
Solution Approach 2:
The method incorporates verification operations between erase loops to detect the state of memory cells and determine whether to continue with additional erase loops. This feedback mechanism allows the system to adaptively control the erase process, performing only the necessary number of loops to achieve the desired threshold voltage distribution, thereby reducing unnecessary complexity while maintaining precision.
3Manufacturing precision
If a post-program operation is performed after erase loops, then the threshold voltage distribution is improved, but the total operation time increases
Solution Approach 1:
The method performs post-program operations after completing the erase loops to improve the threshold voltage distribution. By structuring the process as erase loops followed by post-program operations, the system prepares the memory cells in advance for the final state adjustment. This preliminary action approach allows the main erase operation to complete efficiently while the post-program step fine-tunes the distribution, minimizing the impact on total operation time.
Solution Approach 2:
The method uses periodic verification operations interspersed between erase loops and post-program operations to monitor the threshold voltage distribution. This periodic action allows the system to determine when the desired distribution is achieved and when to terminate further operations, preventing unnecessary time consumption while ensuring the precision goal is met. The periodic structure optimizes the balance between improvement and time loss.
Data Source
AI summary
An operating method of a nonvolatile memory device is provided which sequentially performs a plurality of erase loops to erase at least one of a plurality of memory blocks. The operating method comprises performing at least one of the plurality of erase loops; performing a post-program operation on the at least one memory block after the at least one erase loop is executed; and performing remaining erase loops of the plurality of erase loops. The post-program operation is not performed when each of the remaining erase loops is executed.