Capacitor-Less 1T DRAM Gate Voltage Adjustment
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Solution Overview
Problem
Conventional semiconductor memory devices face limitations in scalability due to capacitor size, leading to the exploration of capacitor-less memory solutions like 1-T DRAM, which require innovative methods to adjust gate voltage levels for effective data storage and retrieval.
Innovation Solution
A method for operating semiconductor devices with a memory cell comprising a drain region, source region, and gate electrode, where a first gate voltage and drain voltage are applied in write mode to change the data state, and an adjustable second gate voltage and drain voltage are applied in hold mode to manage carrier storage in the floating body region, allowing for adjustable voltage levels to optimize data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capacitor is used in conventional memory cells, then data storage capability is improved, but device scalability is worsened due to the large size of the capacitor
Solution Approach 1:
The patent removes the capacitor component from the memory cell structure entirely, transitioning from a conventional 1T1C (one transistor, one capacitor) architecture to a capacitor-less 1T0C design. The floating body region itself serves as the data storage element, eliminating the need for a separate capacitor and thereby reducing the memory cell area while maintaining data storage capability
Solution Approach 2:
The floating body region is designed to serve multiple functions: it acts as both the channel region for transistor operation and the data storage element. By integrating these functions into a single region, the patent eliminates the need for separate capacitor structures, enabling higher density and scalability
2Ease of operation
If gate voltage level is fixed in hold mode, then device operation is simplified, but data retention performance is worsened
Solution Approach 1:
The patent implements dynamic voltage adjustment in the hold mode by introducing a voltage adjustment unit that modifies the gate voltage level based on the detected data state. The system transitions from a static fixed voltage approach to a dynamic adaptive approach where the gate voltage is adjusted to optimal levels for maintaining data integrity during hold operations
Solution Approach 2:
The patent incorporates a feedback mechanism where the sense amplifier detects the data state and provides information to the voltage adjustment unit. This feedback loop enables the system to automatically adjust the gate voltage level in hold mode based on the actual data state, improving data retention performance through adaptive control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient data storage and retrieval by adjusting the amount of carriers stored in the floating body region, enhancing the sense margin and density of memory devices, thereby overcoming scalability limitations.
Implementation Method 1
applying an adjustable second gate voltage to the gate electrode and a second drain voltage to the drain region, in a hold mode after the write mode. The voltage level of the second gate voltage may be adjusted so that an amount of carriers (e.g., holes) stored in the floating body region may be adjusted.
Data Source
AI summary
A method of operating a semiconductor device including a memory cell of a 1-T DRAM is provided in which a gate voltage level in a hold mode is adjusted to adjust a data sensing margin of the semiconductor device.