Dynamic Program Erase Targeting for Memory Endurance
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Solution Overview
Problem
Conventional memory sub-systems experience an imbalance in bit error rate (BER) between logical page types, leading to reduced endurance and earlier end-of-life conditions due to wear, causing an imbalance in read window budget (RWB) and increased error correction triggers.
Innovation Solution
Dynamic program erase targeting (DPET) adjusts the erase distribution voltage based on BER feedback, moving it higher for lower BER signals and lower for higher BER signals, and dithers the voltage level to maintain equilibrium, allowing for optimal placement of programming distributions across all valleys.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory sub-systems use fixed erase distribution voltage, then device complexity is reduced, but bit error rate imbalance occurs between logical page types leading to reduced endurance
Solution Approach 1:
The patent implements dynamic program erase targeting by adjusting the erase distribution voltage based on real-time BER feedback from logical page types. The system transitions from a fixed voltage approach to a dynamic adjustment mechanism that responds to wear conditions, thereby improving endurance without requiring complete system redesign.
Solution Approach 2:
The patent employs feedback control by monitoring BER between logical page types and using this information to adjust the erase distribution voltage. The controller receives BER signals, processes them to determine optimal voltage levels, and dynamically adjusts the voltage to maintain balance between page types, thereby extending device endurance.
2Reliability
If erase distribution voltage is adjusted dynamically based on BER feedback, then bit error rate and trigger rate margin are improved, but device complexity increases due to additional control mechanisms
Solution Approach 1:
The system implements feedback control by monitoring BER between logical page types and using this information to adjust the erase distribution voltage. The controller receives BER signals, processes them to determine optimal voltage levels, and dynamically adjusts the voltage to maintain balance between page types, thereby extending device endurance.
Solution Approach 2:
The patent changes the voltage parameter dynamically based on operational conditions. The controller adjusts the erase distribution voltage level according to BER feedback, transitioning between different voltage states to optimize performance. This parameter adjustment approach improves trigger rate margin while managing system complexity through controlled variability.
3Adaptability or versatility
If fixed program verify targets are used, then manufacturing precision is maintained, but adaptability to die-to-die variations and customer requirements is reduced
Solution Approach 1:
The patent implements dynamic program erase targeting by adjusting the erase distribution voltage based on real-time BER feedback from logical page types. The system transitions from a fixed voltage approach to a dynamic adjustment mechanism that responds to wear conditions, thereby improving endurance without requiring complete system redesign.
Solution Approach 2:
The patent changes the voltage parameter dynamically based on operational conditions. The controller adjusts the erase distribution voltage level according to BER feedback, transitioning between different voltage states to optimize performance. This parameter adjustment approach improves trigger rate margin while managing system complexity through controlled variability.
Data Source
AI summary
A system includes a memory array with memory cells and a processing device coupled thereto. The processing device performs program targeting operations that include to: determine a set of difference error counts corresponding to programming distributions of the memory array; identify, based on a comparison of the set of difference error counts, valley margins corresponding to the programming distributions; select, based on values of the valley margins, a program targeting rule from a set of rules; perform, based on the program targeting rule, a program targeting operation to adjust a voltage level associated with an erase distribution of the memory array; determine a bit error rate (BER) of the memory array; in response to the BER satisfying a BER control value, reduce the voltage level by a voltage step; and in response to the BER not satisfying the BER control value, increase the voltage level by the voltage step.