Adaptive Trim Parameter Transfer in Non-Volatile Memory
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Solution Overview
Problem
As semiconductor flash memory devices scale down, the increasing number of parameters and trim values required for read, program, and erase operations pose challenges in maintaining performance and endurance, leading to area penalties when stored on the memory chip or performance penalties when transferred from the controller.
Innovation Solution
A non-volatile memory system that includes an array of memory cells, data latches, and registers for storing operating parameters, where a specified command sequence loads these parameters into data latches and transfers them to registers before executing read/write/erase operations, allowing for adaptive trimming without area or time penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If operating parameters are stored on the memory chip in registers, then the memory circuit can access parameters quickly, but a large area penalty is incurred due to the increasing number of parameters
Solution Approach 1:
The patent extracts the operating parameters from the memory chip and stores them externally in the controller. Only essential control logic remains on the memory chip, while the parameter storage is moved to the controller's memory resources, eliminating the area penalty on the memory chip while maintaining fast access through direct control logic connection.
Solution Approach 2:
The controller's memory resources are used for dual purposes: storing operating parameters and maintaining normal memory operations. This multi-functional use of the controller's memory eliminates the need for dedicated parameter storage on the memory chip, reducing area requirements while preserving access speed.
2Area of stationary object
If operating parameters are kept on the controller and transferred to the memory circuit, then the memory chip area is preserved, but a performance penalty is incurred due to transfer time
Solution Approach 1:
The controller prepares and transfers operating parameters to the memory circuit in advance, before the actual memory operations are needed. This preliminary action ensures that parameters are already available in the memory circuit when operations commence, eliminating transfer delays during critical operations and maintaining high productivity.
3Reliability
If the number of parameters is increased to meet endurance and performance requirements of scaled devices, then device reliability is improved, but the complexity of the system increases
Solution Approach 1:
The memory circuit includes self-contained control logic that can independently manage and apply operating parameters received from the controller. This self-service capability allows the memory circuit to handle increased parameter counts without proportionally increasing system complexity, as the parameters are managed locally rather than requiring complex external coordination.
Data Source
AI summary
As memory devices scale down, the controller may use different sets of trim values for read/program/erase operations for different blocks based on the amount of wear a block has experienced. To facilitate this process, when the controller issues series of commands, a set of parameters for the operations are initially transferred into latches that are normally used for user data, after which they are transferred into the registers used to hold the parameters while the operation is performed. This allows for read, write and erase parameters to be updated with minimal time penalty and on the fly, allowing for these trim values to be changed more frequently and without the need to add extra registers on the memory circuit.