NAND Flash Read Voltage Adjustment via Bitwise Pairing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Multi-level cell (MLC) NAND flash memory devices experience reduced read/write/erase performance compared to single-level cell (SLC) devices due to broadened threshold voltage distributions, leading to read errors, necessitating adjustments in read voltages to improve data reliability.
Innovation Solution
A method of adjusting read voltages by simultaneously changing test read voltages and performing bitwise operations on paired page data to set optimal read voltages corresponding to sections with the lowest change in memory cells, thereby minimizing read errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MLC NAND flash memory device stores multi-bit data per memory cell, then storage capacity increases and chip size reduces, but read/write/erase performance deteriorates
Solution Approach 1:
The patent segments the read voltage adjustment process into multiple discrete voltage levels (first read voltage, second read voltage, third read voltage) corresponding to different threshold voltage states. By dividing the voltage range into sections and adjusting each read voltage independently based on threshold voltage distribution characteristics, the patent enables precise reading of multi-bit data stored in MLC memory cells, thereby improving read performance while maintaining high storage capacity.
2Quantity of substance
If MLC NAND flash memory device stores multi-bit data per memory cell, then storage capacity increases, but read error rate increases due to broadened threshold voltage distribution
Solution Approach 1:
The patent dynamically changes read voltage parameters (first read voltage, second read voltage, third read voltage) based on the broadened threshold voltage distribution caused by charge loss and acquisition. By adjusting the voltage levels and their corresponding sections according to actual threshold voltage states, the patent compensates for distribution broadening effects, reducing read errors while maintaining multi-bit storage capability.
3Measurement precision
If read voltages are adjusted separately for each page, then voltage precision improves, but adjustment time increases
Solution Approach 1:
The patent merges the adjustment process of multiple read voltages into a unified operation. By simultaneously determining the first read voltage, second read voltage, and third read voltage based on a single threshold voltage distribution analysis, the patent achieves precise voltage adjustment for multiple pages without requiring separate adjustment procedures, thereby reducing overall adjustment time while maintaining voltage precision.
Data Source
AI summary
A method of adjusting read voltages for a NAND flash memory device includes an operation of reading first page data from a first page corresponding to a paired page of a second page, an operation of simultaneously changing the first test read voltage and the third test read voltage to read second page data from a second page, an operation of performing a bitwise operation on the first page data and the second page data an operation of counting a number of memory cells corresponding to a first threshold voltage state and a fourth threshold voltage state by using a result of the bitwise operation, and an operation of setting a first read voltage and a third read voltage as a voltage corresponding to a section in which a change in the number of memory cells is a lowest value.