Parallel MOS Transistor Data Latch Circuit for Memory Reliability
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Solution Overview
Problem
Current semiconductor memory devices face challenges in enhancing the robustness of data input and output operations due to instability in data latch circuits, which can lead to failures in data transfer between sense amplifiers and input/output circuits.
Innovation Solution
The semiconductor memory device incorporates multiple MOS transistors, including at least three N-channel type and one P-channel type MOS transistors connected in parallel, or vice versa, between the data storage unit and data wiring to improve data latch circuit stability and robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple MOS transistors are connected in parallel between data storage unit and data wiring, then reliability of data transfer is improved, but device complexity increases
Solution Approach 1:
The patent divides the single transistor function into multiple parallel transistors (at least three N-channel and one P-channel, or vice versa), creating segmented redundant pathways for data transfer. This segmentation ensures that if one transistor fails, others can maintain operation, directly resolving the reliability improvement while managing complexity through functional division.
Solution Approach 2:
The patent implements beforehand cushioning by pre-configuring redundant transistor pathways before any failure occurs. The multiple parallel transistors serve as preemptive backups, cushioning against potential single-transistor failures and ensuring continuous data transfer capability without requiring real-time fault detection or system reconfiguration.
2Reliability
If multiple MOS transistors are used in parallel configuration, then robustness of data input/output is improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into standardized transistor unit fabrication, where identical N-channel and P-channel transistors are manufactured using the same process steps. This segmentation allows for modular assembly of the parallel transistor configuration, reducing overall manufacturing complexity despite the increased number of components.
Solution Approach 2:
The patent uses homogeneous transistor designs within each channel type (all N-channel or all P-channel transistors have identical characteristics), allowing for standardized manufacturing processes. This homogeneity simplifies fabrication by enabling batch production of identical transistor units that can be systematically arranged in parallel configurations.
Data Source
AI summary
A semiconductor memory device includes a plurality of data latch circuits that are used for input and output of data between a sense amplifier circuit and an input/output circuit, and a data bus that is connected to the plurality of data latch circuits. Each of the data latch circuits includes an inverter circuit that temporarily stores data input and output between the sense amplifier circuit and the input/output circuit, and at least three MOS transistors between the inverter circuit and the data bus. The at least three MOS transistors may be multiple N-channel type MOS transistors and at least one P-channel type MOS transistor connected in parallel between the inverter circuit and the data bus, or at least one N-channel type MOS transistor and multiple P-channel type MOS transistors connected in parallel between the inverter circuit and the data bus.