Nonvolatile Memory Address Re-mapping for Defect Tolerance
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Solution Overview
Problem
As memory cell sizes decrease to achieve high integration in nonvolatile memory devices, the complexity of operation circuit structures and wirings can degrade electrical characteristics, leading to a demand for devices with high integration and excellent electrical performance while maintaining performance and reducing chip size.
Innovation Solution
A nonvolatile memory device with a memory cell region and a peripheral circuit region, featuring a control circuit that groups memory sub-blocks based on physical and electrical characteristics, performs address re-mapping by replacing defective sub-blocks with non-defective ones within the same group, maintaining performance while reducing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell sizes are decreased to achieve high integration, then integration density is improved, but electrical characteristics are degraded due to increased complexity of operation circuits and wirings
Solution Approach 1:
The memory device is divided into multiple memory blocks, each containing multiple memory sub-blocks. This segmentation allows the system to manage complexity by organizing memory cells into smaller, more manageable units that can be independently controlled and tested, thereby maintaining electrical characteristics while achieving high integration density.
Solution Approach 2:
The patent employs a three-dimensional vertical structure with through-hole vias extending through multiple layers to connect memory blocks. This dimensional approach allows for increased integration density without proportionally increasing wiring complexity in the planar direction, as connections are established through the vertical dimension, thereby preserving electrical characteristics while achieving high integration.
2Reliability
If address re-mapping is performed by replacing defective memory sub-blocks, then reliability is improved, but device complexity increases due to additional control circuit functions
Solution Approach 1:
The control circuit pre-establishes mapping relationships between memory blocks and sub-blocks during initialization or manufacturing testing. Defective sub-blocks are identified in advance and mapped to alternative non-defective sub-blocks before actual memory operations begin. This preliminary action allows the system to achieve defect tolerance without adding complex real-time decision-making logic during normal operation.
Solution Approach 2:
The patent creates redundant copies of memory sub-blocks that can serve as replacements for defective ones. By having duplicate or alternative sub-blocks available within the same memory block, the system can replace defective units with their copies, achieving reliability improvement through redundancy rather than through complex control logic.
Data Source
AI summary
A nonvolatile memory device includes memory cell region including a first metal pad and a peripheral circuit region including a second metal pad, is connected to the memory cell region by the first metal pad and the second metal pad and includes including an address decoder and a page buffer circuit located on a first substrate. A memory cell array is provided in the memory cell region, which includes a first vertical structure on a second substrate. The first vertical structure includes first sub-blocks and first via areas in which one or more through-hole vias are provided, and through-hole vias pass through the first vertical structure. A control circuit in the peripheral circuit region groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.