1T Compact ROM Cell with Dual Bit Storage
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Solution Overview
Problem
Single transistor ROM bitcells face challenges in achieving high density and speed while maintaining low voltage operation, as small device widths lead to increased variability and reduced reliability, and larger widths compromise density.
Innovation Solution
The implementation of a ROM memory device with a virtual ground generation circuit and bit line pairs that allow bit lines to function as both data lines and virtual ground lines, enabling the storage of two bits of data in a single transistor with improved density and speed by controlling polarities and using column multiplexers to read data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device width is reduced to increase density, then storage density is improved, but variability increases and reliability decreases
Solution Approach 1:
The patent combines two bit storage functions into a single transistor by utilizing both the channel and diffusion region, effectively merging storage capabilities to increase density without reducing device dimensions. This allows one transistor to store two bits through clever use of the transistor's structural regions.
Solution Approach 2:
The bit line serves multiple functions: it acts as both a data readout line and a virtual ground line depending on the read operation. This multi-functionality reduces the number of required lines and allows the same physical infrastructure to support dual-bit storage operations.
2Reliability
If device width is increased to improve speed and reduce variability, then reliability is improved, but storage density decreases
Solution Approach 1:
The patent merges two bit storage functions into a single transistor by utilizing both the channel and diffusion region, effectively merging storage capabilities to increase density without reducing device dimensions. This allows one transistor to store two bits through clever use of the transistor's structural regions.
Solution Approach 2:
The patent transitions from storing one bit per transistor to storing two bits per transistor by utilizing an additional spatial dimension within the transistor structure (the diffusion region). This dimensional utilization increases storage capacity without requiring additional transistors or larger device footprints.
3Device complexity
If virtual ground line is shared between bit line pairs, then device complexity is reduced, but control precision requirements increase
Solution Approach 1:
The bit line serves multiple functions: it acts as both a data readout line and a virtual ground line depending on the read operation. This multi-functionality reduces the number of required lines and allows the same physical infrastructure to support dual-bit storage operations.
Solution Approach 2:
The system dynamically switches the role of bit lines between data readout and virtual ground functions based on which bit is being read. This dynamic reconfiguration allows the same physical lines to serve different purposes at different times, reducing overall device complexity.
Data Source
AI summary
Disclosed is a ROM memory device including a plurality of rows and columns of memory cells, each memory cell including a bit line pair and a transistor to store two bits of data therein, and a virtual ground line disposed between adjacent pairs of bit line pairs, wherein the bit line pair and virtual ground line are used to read data stored in the memory cells.