Bit Line Pre-Charging for Memory Read Error Reduction
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Solution Overview
Problem
Non-volatile memory devices face challenges in maintaining accurate read levels due to threshold voltage drift over time, leading to increased read errors and the need for dynamic read level adjustments, which are complicated by manufacturing variations and interference effects.
Innovation Solution
A memory apparatus and method that pre-charge specific bit lines associated with subsets of memory cells to minimize read errors, using a controller to determine optimal read levels by comparing results at different reference levels and adjusting the read level to minimize misreads, thereby accounting for variations in memory hole types and strings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dynamic read level adjustments are implemented to compensate for threshold voltage drift, then read accuracy is improved, but device complexity increases
Solution Approach 1:
The patent performs preliminary scanning operations to identify optimal read levels before actual data reading. The controller scans through multiple reference levels to detect threshold voltage drift and determines the optimal read level in advance, which is then used for subsequent read operations. This preliminary action eliminates the need for complex real-time adjustments during data reading.
Solution Approach 2:
The memory device performs self-diagnosis and self-adjustment by scanning its own threshold voltage distribution and automatically determining optimal read levels. The controller monitors read errors and adjusts read levels autonomously without requiring external intervention or complex external control circuits.
2Manufacturing precision
If threshold voltage ranges are maintained with gaps between data states, then manufacturing precision is improved, but loss of information increases due to threshold voltage drift
Solution Approach 1:
The patent implements a feedback mechanism where the controller continuously monitors read operations and detects read errors caused by threshold voltage drift. Based on this feedback, the controller adjusts the read level dynamically to maintain optimal reading conditions even when threshold voltage ranges drift over time, preventing data loss without requiring tighter manufacturing tolerances.
3Reliability
If bit lines are pre-charged to minimize read errors, then reliability is improved, but use of energy increases
Solution Approach 1:
The patent applies pre-charging selectively only to bit lines that are likely to experience read errors due to threshold voltage drift, rather than pre-charging all bit lines uniformly. The controller identifies specific bit lines or memory regions that benefit from pre-charging based on detected error patterns, thereby reducing overall energy consumption while maintaining reliability where needed.
Data Source
AI summary
A memory apparatus and operating method are provided. The apparatus includes memory cells connected to one of a plurality of word lines and disposed in memory holes coupled to bit lines. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the bit lines and for a group of the memory cells divided into a plurality of subsets, is configured to determine whether comparatively fewer read errors of the memory cells arise while pre-charging ones of the bit lines associated with each of the plurality of subsets. The control means is also configured to pre-charge ones of the bit lines associated with one the plurality of subsets with comparatively fewer read errors and read the memory cells associated therewith during a scan operation.