Data Loading Circuit Area Reduction via Segmented Storage

Solution Overview

Problem

The existing data loading circuits in semiconductor devices require a large area for shift registers due to the need for master and slave latches, which increases as the quantity of data to be loaded increases, reducing the design margin of electronic devices.

Innovation Solution

A data loading circuit comprising a non-volatile memory, a deserializer, a load controller, and a loading memory unit that outputs a serial data signal and generates sequential loading selection signals to store data bits in a loading memory unit, reducing the area required for data storage by using a shift register for temporary shifting and a loading memory for permanent storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a shift register with master latch and slave latch is used to store data bits, then data storage capability is provided, but the occupied area increases significantly

Engineering Contradiction:

Improvedata storage capabilityVSAvoidoccupied area

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

The data loading circuit is divided into multiple loading units, each responsible for loading a specific group of data bits. Each loading unit contains a loading register that is activated sequentially by loading selection signals. This segmentation allows the system to load data in batches rather than requiring all data bits to be stored simultaneously in a single large shift register, thereby reducing the peak area requirement.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Data bits are loaded into the loading registers in advance during the data loading phase before the data output phase begins. The loading selection signals are generated in advance to activate each loading unit at the appropriate time. This preliminary action allows the system to prepare data for output without requiring all data to be held in large buffers simultaneously, reducing the area needed for data storage structures.

Inventive Principle:

Principle #10Preliminary action

2Quantity of substance

If the quantity of data to be loaded increases, then data capacity is improved, but the required area of the shift register increases accordingly

Engineering Contradiction:

Improvedata capacityVSAvoidshift register area

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

The data loading circuit is divided into multiple loading units, each responsible for loading a specific group of data bits. Each loading unit contains a loading register that is activated sequentially by loading selection signals. This segmentation allows the system to load data in batches rather than requiring all data bits to be stored simultaneously in a single large shift register, thereby reducing the peak area requirement.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The data loading process is divided into multiple periodic phases, with each phase corresponding to a specific loading unit being activated. The load controller generates loading selection signals in a periodic sequence, activating one loading unit at a time. This periodic action allows data to be loaded in successive time intervals, reducing the area requirement compared to loading all data simultaneously.

Inventive Principle:

Principle #19Periodic action

3Quantity of substance

If a large area shift register is used to accommodate increased data quantity, then data loading capacity is improved, but the design margin of the electronic device decreases

Engineering Contradiction:

Improvedata loading capacityVSAvoiddesign margin

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The data loading circuit is divided into multiple loading units, each responsible for loading a specific group of data bits. Each loading unit contains a loading register that is activated sequentially by loading selection signals. This segmentation allows the system to load data in batches rather than requiring all data bits to be stored simultaneously in a single large shift register, thereby reducing the peak area requirement.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Data bits are loaded into the loading registers in advance during the data loading phase before the data output phase begins. The loading selection signals are generated in advance to activate each loading unit at the appropriate time. This preliminary action allows the system to prepare data for output without requiring all data to be held in large buffers simultaneously, reducing the area needed for data storage structures.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS9384861B2Data loading circuit and semiconductor memory device comprising same

Publication Date: 2016.07.05 SAMSUNG ELECTRONICS CO LTD

AI summary

A data loading circuit comprises a non-volatile memory configured to store non-volatile data and output a serial data signal based on the stored non-volatile data in response to a power-up operation, a deserializer configured to receive the serial data signal and output multiple data bits at intervals of a unit period based on the received serial data signal, a load controller configured to generate multiple loading selection signals that are sequentially activated one-by-one at each interval of the unit period, and a loading memory unit configured to sequentially store the data bits at each interval of the unit period in response to the loading selection signals.