Semiconductor Memory Bank Address Counter Power Reduction
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Solution Overview
Problem
Semiconductor memory devices face high power consumption during data output operations, which is a challenge in maintaining efficiency and performance, especially in portable electronic devices.
Innovation Solution
The semiconductor memory device incorporates a dual-memory bank system with address counters and output control units that generate column address signals and strobe signals to optimize data output, enabling alternation of data output between memory banks and reducing power consumption by disabling one address counter during data output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If both address counters operate during data output operation, then data transfer speed is maintained, but power consumption increases
Solution Approach 1:
The memory system is divided into multiple memory banks (first memory bank and second memory bank), each with its own address counter. During data output operations, only the address counter corresponding to the active memory bank is enabled, while the other is disabled. This segmentation allows selective operation of address counters, reducing overall power consumption while maintaining data transfer capability through the active bank.
Solution Approach 2:
The patent implements alternating operation between first and second memory banks. During data output operations, the system periodically switches between banks, enabling one address counter while disabling the other. This periodic alternation ensures that data transfer continues through the active bank while the inactive bank's address counter consumes minimal power, resolving the contradiction between power consumption and data transfer speed.
2Productivity
If dual address counters are used for both memory banks, then data output performance is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic control of address counters through output control units that selectively enable or disable the first and second address counters based on the operational mode. During data output operations, the system dynamically activates only the required address counter, reducing the active device complexity while maintaining the capability for high-performance data output when both banks are operational.
Solution Approach 2:
Both address counters are designed with universal functionality to handle addressing for their respective memory banks in both data input and data output operations. This multi-functionality allows the system to maintain high data output performance using the same address counter infrastructure, reducing the need for additional specialized components and thereby limiting the increase in device complexity.
3Loss of energy
If one address counter is disabled during data output, then power consumption is reduced, but addressing capability for first memory bank is lost
Solution Approach 1:
During data output operations, the patent extracts or isolates the addressing function to only the active memory bank's address counter. The first address counter is disabled when the second memory bank is active for data output, removing the unnecessary addressing capability from the first memory bank during this specific operation. This extraction reduces power consumption while the active bank maintains full addressing capability through its dedicated counter.
Solution Approach 2:
The patent applies local quality by enabling addressing capability only where needed during data output operations. When the second memory bank is active, the second address counter provides full addressing capability locally, while the first address counter is disabled. This localized addressing ensures that the necessary versatility is maintained in the active region while power consumption is reduced in the inactive region.
Data Source
AI summary
A semiconductor memory device includes a first memory bank and a second memory bank; an address counter unit including: a first address counter suitable for outputting a first counting address signal corresponding to the first memory bank; and a second address counter suitable for outputting a second counting address signal corresponding to the second memory bank; a first output control unit suitable for generating first column address signals in response to the first counting address signal during a data input operation, and generating the first column address signals in response to the second counting address signal during a data output operation; and a second output control unit generating second column address signals in response to the second counting address signal during the data input operation and the data output operation.