Consecutive Verification for Non-Volatile Memory Write Performance
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Solution Overview
Problem
Non-volatile memory devices face challenges in improving write performance due to the time-consuming process of programming and verifying data, which affects the capacity and speed of storage devices in consumer electronics and cloud computing applications.
Innovation Solution
The implementation of consecutive verification operations in data storage systems, where multiple memory cells are programmed and verified simultaneously, reducing the need for repeated word line voltage ramping and optimizing the timing of program and verify cycles by overlapping data latch usage and sensing phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional sequential programming and verification operations are performed in non-volatile memory devices, then data accuracy and error correction are maintained, but write performance and programming speed deteriorate due to time-consuming operations
Solution Approach 1:
The patent applies preliminary action by performing verification operations on multiple memory cells simultaneously during the programming process, rather than waiting for all programming to complete. The verification unit checks programmed data in parallel with ongoing programming operations, and data latches pre-load and hold verification results, allowing the system to advance to the next programming phase without waiting for sequential verification of each cell.
Solution Approach 2:
The patent implements continuity of useful action by overlapping programming and verification operations in time. Multiple verification operations occur concurrently with programming operations on different memory cells, eliminating idle time between programming and verification. The data latch maintains verification results continuously available, ensuring the useful action of data validation proceeds without interruption while programming continues.
2Speed
If multiple memory cells are programmed and verified simultaneously using consecutive verification operations, then programming speed and write performance improve, but device complexity increases due to additional verification units and data latches
Solution Approach 1:
The verification unit is designed with multi-functionality to handle verification operations across multiple memory cells simultaneously. Rather than requiring separate verification circuits for each memory cell, a single universal verification unit can verify multiple cells in parallel by switching between them, reducing overall device complexity while maintaining high-speed parallel verification capabilities.
Solution Approach 2:
The patent uses data latches to create temporary copies of programmed data for verification purposes. Instead of repeatedly accessing the actual memory cells during verification, the system copies data into latch circuits that hold the values, allowing fast verification without complex repeated access mechanisms. This copying approach simplifies the verification pathway while enabling parallel operations.
3Reliability
If verification operations are performed repeatedly on the same memory cells, then data accuracy is ensured, but programming time increases due to multiple programming-verification cycles
Solution Approach 1:
The patent performs preliminary verification on multiple memory cells in parallel during the programming process itself, rather than conducting repeated sequential verification cycles after programming completes. By verifying data as it is being programmed across multiple cells simultaneously, the system ensures data accuracy early in the process and identifies errors that can be corrected without requiring multiple complete programming-verification cycles.
Solution Approach 2:
The continuous overlapping of programming and verification operations ensures that validation occurs throughout the programming process rather than requiring repeated discrete cycles. The verification unit continuously checks programmed data while programming proceeds, maintaining uninterrupted useful action that ensures data accuracy without extending total programming duration through repeated cycles.
Data Source
AI summary
A data storage system includes a storage medium including a plurality of strings of single-level cell (SLC) memory cells connected to a plurality of word lines; and a storage controller in communication with the storage medium, the storage controller including write circuitry configured to write data to the storage medium by: selecting a first word line of the plurality of word lines, the first word line being connected to a first plurality of strings; consecutively programming a first group of memory cells of the first plurality of strings connected to the first word line; and subsequent to programming the first group of memory cells, consecutively verifying respective programming results of the first group of memory cells.