Hierarchical Word Line Voltage Control for GIDL Suppression
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Solution Overview
Problem
In semiconductor memory devices, particularly DRAMs, the Gate Induced Drain Leakage (GIDL) current in P-channel MOS transistors is significant, contributing to high current consumption during standby states and posing reliability risks due to strong electric fields at the gate oxide film, which existing technologies struggle to adequately suppress.
Innovation Solution
The semiconductor memory device employs a hierarchical word line structure with a voltage switching circuit that sets the high level of non-selected main word lines to a lower boost voltage, reducing the electric field at the gate oxide film of PMOS transistors, thereby suppressing GIDL current across multiple sub-word drivers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the boost voltage VPP is sufficiently reduced to suppress GIDL current, then the GIDL current is reduced, but the circuit operation of the main word driver cannot be maintained
Solution Approach 1:
The patent divides the word line control into hierarchical segments: main word lines and sub-word lines. The main word driver controls main word lines with higher voltage for strong drive capability, while sub-word drivers control sub-word lines with lower voltage to suppress GIDL current. This segmentation allows different voltage levels to be applied to different parts of the word line structure, resolving the contradiction between maintaining circuit operation and reducing GIDL current.
Solution Approach 2:
The patent applies different voltage characteristics to different locations in the word line hierarchy. The main word lines receive high boost voltage VPP for strong switching capability, while the sub-word lines receive lower voltage to minimize GIDL current. This local differentiation of voltage quality allows the system to maintain operational effectiveness where needed while suppressing harmful effects where possible.
2Reliability
If the boost voltage VPP is applied to gates of PMOS transistors to bring them into OFF state, then the transistors are properly switched, but GIDL current inevitably flows
Solution Approach 1:
The transistor control is segmented into two levels: main word driver transistors that require high voltage for reliable switching, and sub-word driver transistors that operate at lower voltage. By separating the switching functions into these two hierarchical levels, the system can maintain reliable transistor operation where high voltage is necessary while using lower voltage elsewhere to prevent GIDL current generation.
Solution Approach 2:
The patent dynamically adjusts the voltage applied to different word line levels based on operational requirements. The main word lines use high voltage VPP when active, while sub-word lines use lower voltage to suppress GIDL. This dynamic voltage adjustment allows the system to optimize between switching reliability and GIDL suppression depending on the operational context.
3Ease of operation
If a strong electric field E occurs at the gate oxide film of PMOS transistor, then the transistor switching is effective, but the reliability of the gate oxide film decreases
Solution Approach 1:
The patent applies different electric field strengths to different locations in the word line hierarchy. The main word driver experiences stronger electric fields for effective switching, while the sub-word drivers operate with weaker electric fields that are sufficient for switching but below the threshold that would damage the gate oxide film. This local differentiation protects the gate oxide film from degradation while maintaining switching effectiveness.
Solution Approach 2:
The system dynamically controls the electric field strength applied to different word line levels. During normal operation, the main word lines experience high electric fields for effective switching, while sub-word lines experience reduced electric fields that balance switching effectiveness with gate oxide film protection. This dynamic control prevents cumulative damage to the gate oxide film over time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces GIDL current, leading to lower overall current consumption in the memory device and enhances the reliability of the PMOS transistors by minimizing the electric field at the gate oxide film, significantly reducing current during standby states and improving device reliability.
Implementation Method 1
suppressing GIDL (Gate Induced Drain Leakage) current, which is included in the leak current, flowing through a P-channel MOS transistor
Implementation Method 2
The magnitude of the GIDL current changes exponentially relative to an electric field E generated at the gate oxide film 104, on the basis of the boost voltage VPP
Data Source
AI summary
A semiconductor memory device comprises a memory cell array having a hierarchical word line structure including main word lines and sub-word lines; a main word driver for driving a non-selected main word line to high and for driving and activating a selected main word line to low; and a sub-word driver having a PMOS transistor whose gate is connected to the main word line for selectively activating the sub-word line corresponding to the selected main word line. The memory cell array is divided into a plurality of areas which is controlled such that a high level of each main word line is set to a first boost voltage in a predetermined area including the selected main word line, and a high level of each main word line is set to a second boost voltage lower than the first boost voltage in the other area.