NAND Flash Page Buffer Voltage Control for MLC Programming
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Solution Overview
Problem
In NAND flash memory applications, existing page buffer designs face challenges in efficiently programming and reading data from Multi-Level Cell (MLC) memory cells, particularly in ensuring accurate programming and reading of both lower and upper page bits, which affects storage density and cost-effectiveness.
Innovation Solution
A page buffer circuit with a data change unit that alters the latch voltage to a high level, enabling programming and reading of lower and upper page bits only when the latch value is high, and includes a program control unit to manage bit programming and reading across multiple voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a traditional page buffer design is used for MLC memory, then the circuit structure is simple, but the programming and reading performance is insufficient
Solution Approach 1:
The page buffer circuit is segmented into multiple functional units including a first latch for storing lower page data, a second latch for storing upper page data, and a data change unit for voltage level conversion. This segmentation allows independent optimization of each unit's function, improving overall programming and reading performance while maintaining manageable circuit complexity.
Solution Approach 2:
The data change unit acts as an intermediary between the latches and the memory cells, converting voltage levels to enable proper programming operations. This intermediary component resolves the voltage level mismatch between different page data representations, enhancing the buffer's ability to handle MLC memory operations efficiently.
2Reliability
If the latch voltage is not changed to high level, then the circuit operation is straightforward, but accurate programming and reading of both lower and upper page bits cannot be ensured
Solution Approach 1:
The data change unit performs preliminary voltage level conversion on the latch data before programming operations begin. By pre-converting lower page data to high voltage levels, the system ensures accurate programming and reading without requiring complex real-time voltage control during the actual memory operations.
Solution Approach 2:
The invention changes the voltage level parameter of the latch data dynamically based on the page type (lower or upper). The data change unit transforms the voltage parameter from low level to high level when needed, enabling reliable distinction and handling of different page data without complicating the overall control mechanism.
3Quantity of substance
If MLC technology is used to store multiple bits per cell, then storage density increases and cost per megabyte decreases, but the page buffer design becomes more challenging
Solution Approach 1:
The page buffer circuit is designed with universal functionality to handle both lower page and upper page data through a unified structure. The first and second latches, along with the data change unit, work together to manage multiple bits per cell in MLC memory, achieving high storage density without proportionally increasing circuit complexity.
Data Source
AI summary
A page buffer and method of programming and reading a memory are provided. The page buffer includes a first latch, a second latch, a data change unit and a program control unit. The first latch includes a first terminal for loading data of the lower page and the upper page. The second latch includes a first terminal for storing the data of the lower page and the upper page from the first latch. The data change unit is coupled to a second terminal of the first latch for changing a voltage of the second terminal of the first latch to a low level. The program control unit is coupled to the first terminal of the second latch and the cells, and controlled by the voltage of the first terminal of the first latch for respectively programming the data of the lower page and the upper page to a target cell.