Reducing Read Disturb in Partially Written NAND Blocks
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Solution Overview
Problem
In NAND-type non-volatile memory systems, determining the last written word line in a partially written block is challenging due to high bit error rates caused by read disturb and capacitive coupling, leading to inefficiencies in data retrieval and storage.
Innovation Solution
A method is introduced that applies a reduced sensing voltage (VREAD_PARTIAL) on non-selected word lines during the sensing operation, allowing memory cells to conduct independently of their data state, which reduces bit error rates and minimizes read disturb by using a lower voltage level for unwritten word lines, thereby accelerating the detection of the last written word line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a standard sensing voltage is applied to non-selected word lines during sensing operation, then memory cells can be reliably sensed, but read disturb increases and bit error rates increase in partially written blocks
Solution Approach 1:
The patent applies different voltage levels to non-selected word lines based on their position relative to the selected word line. Specifically, a first voltage level (higher) is applied to non-selected word lines on one side of the selected word line, while a second voltage level (lower) is applied to non-selected word lines on the other side. This local differentiation reduces read disturb on erased word lines while maintaining sufficient conduction for sensing operations.
Solution Approach 2:
The patent changes the voltage parameter applied to non-selected word lines during sensing operations. By reducing the voltage level on certain non-selected word lines (making it less than the threshold voltage of programmed cells), the patent minimizes read disturb effects while still allowing erased word lines to conduct sufficiently for detection purposes.
2Speed
If multiple word lines are read in parallel during sensing, then sensing speed is improved, but capacitive coupling between word lines increases causing bit error rates to increase
Solution Approach 1:
The patent differentiates the voltage treatment of non-selected word lines based on their spatial relationship to the selected word line. By applying lower voltage levels to specific non-selected word lines that are more susceptible to capacitive coupling effects, the patent reduces bit error rates while maintaining parallel sensing capability across multiple word lines.
3Ease of operation
If the sensing operation uses standard voltage levels on all word lines, then the sensing circuit operation is simplified, but detection accuracy of the last written word line decreases
Solution Approach 1:
The patent implements differentiated voltage levels on non-selected word lines to improve detection accuracy. By applying a lower voltage level (second voltage level) to non-selected word lines that are less likely to conduct, the patent enhances the ability to distinguish between programmed and erased states, thereby improving detection accuracy of the last written word line.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces bit error rates and improves the accuracy of last written page detection, enhancing the performance and reliability of data retrieval in partially written blocks by minimizing the disturbance on erased word lines.
Implementation Method 1
determining the last written word line in a partially written block is challenging due to high bit error rates caused by read disturb and capacitive coupling
Data Source
AI summary
Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for data read. In both cases, non-selected word lines that are unwritten or, in the case of finding the last written word line, may be unwritten are biased with a lower read-pass voltage then is typically used. The result of such reads can also be applied to an algorithm for finding the last written word by skipping a varying number of word lines. Performance in a last written page determination can also be improved by use of shorter bit line settling times than for a standard read.