NAND Flash Memory Read Biasing for Capacitive Coupling
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Solution Overview
Problem
High integration in NAND-type flash memory leads to increased capacitive coupling between adjacent cells, causing unreliable data read operations due to insufficient cell current and prolonged sensing time, especially for unselected cells on the source line side.
Innovation Solution
The implementation of a data read mode with specific bias conditions, where unselected word lines on the bit line side are applied with a first read pass voltage, and those on the source line side are applied with a third read pass voltage higher than the first, to suppress capacitive coupling effects and ensure sufficient cell current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If unselected word lines are applied with a uniform read pass voltage, then the device structure and control logic are simple, but the capacitive coupling between adjacent cells causes insufficient cell current and unreliable data read operations
Solution Approach 1:
The patent applies different read pass voltages to different groups of unselected word lines based on their position relative to the selected word line. Specifically, unselected word lines on the bit line side receive a first read pass voltage, while unselected word lines on the source line side receive a third read pass voltage that is higher than the first. This local differentiation compensates for the asymmetric capacitive coupling effects, ensuring sufficient cell current flow and reliable data read operations without requiring complete redesign of the control system.
Solution Approach 2:
The patent changes the voltage parameter (read pass voltage) applied to unselected word lines based on their position. By adjusting the voltage level - using a higher third read pass voltage for source line side word lines compared to the first read pass voltage for bit line side word lines - the patent compensates for position-dependent capacitive coupling effects, thereby improving read reliability while maintaining manageable control complexity through systematic parameter variation.
2Quantity of substance
If high integration is implemented in NAND-type flash memory, then the storage capacity increases, but the capacitive coupling between adjacent cells increases causing cell current decrease and prolonged sensing time
Solution Approach 1:
The patent addresses the reliability issue arising from high integration by applying different read pass voltages to different spatial regions of unselected word lines. The bit line side unselected word lines receive a first read pass voltage, while source line side unselected word lines receive a higher third read pass voltage. This local quality differentiation compensates for the position-dependent capacitive coupling effects that become more pronounced with higher integration, ensuring sufficient cell current and reliable data read operations.
3Productivity
If unselected cells operate as pass transistors with standard read pass voltage, then the read operation is simple, but the negative feedback in lower course side cells causes high channel resistance and cell current decrease
Solution Approach 1:
The patent resolves the contradiction between read operation simplicity and cell current sufficiency by applying different read pass voltages to different groups of unselected word lines. The source line side unselected word lines, which are prone to negative feedback effects and high channel resistance, receive a higher third read pass voltage. This local enhancement ensures these cells can still operate effectively as pass transistors without compromising overall read operation efficiency or reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of data read operations by increasing the read margin and reducing sensing time, while maintaining the integrity of cell data.
Implementation Method 1
the capacitive coupling between adjacent cells influences the read operation
Data Source
AI summary
A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage.