Phase Change Memory Column Decoder Using Parallel PMOS NMOS Sub-Blocks
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Solution Overview
Problem
Existing CMOS memory structures cannot efficiently apply an erase or programming voltage close to the maximum technological voltage to phase change memory cells without using high-voltage transistors and cannot apply a low-value read voltage without complex and costly architecture, including negative voltage charge pumps.
Innovation Solution
The integration circuit employs a memory cell selection circuit with parallel sub-blocks of PMOS and NMOS transistors to independently manage erase/programming and read voltages, allowing for the application of high erase/programming voltages and low read voltages without high-voltage transistors or negative gate voltages, using identical selection signals to control the sub-blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high erase or programming voltage close to the maximum technological voltage is applied to phase change memory cells, then the erase or programming function is achieved, but high-voltage transistors are required which increase device complexity and manufacturing cost
Solution Approach 1:
The memory array is divided into multiple blocks, each block containing memory cells that can be independently selected and operated. This segmentation allows the high voltage to be applied only to selected blocks rather than the entire array, reducing the complexity of voltage distribution and enabling the use of standard transistors in non-selected areas.
Solution Approach 2:
A voltage translation circuit is introduced as an intermediary between the standard voltage supply and the memory cells. This circuit translates the standard voltage to the required high voltage for erase or programming operations, eliminating the need for high-voltage transistors while maintaining the necessary voltage levels for reliable operation.
2Reliability
If a low-value read voltage is applied to memory cells, then reading is conducted without modifying the state of the memory point, but complex architecture including negative voltage charge pumps is required
Solution Approach 1:
The same voltage translation circuit used for high-voltage erase/programming operations is also utilized for low-voltage read operations. This multi-functional approach eliminates the need for separate negative voltage charge pumps, reducing device complexity while maintaining the ability to apply precise low read voltages without modifying memory cell states.
Solution Approach 2:
The voltage translation circuit automatically adjusts its output voltage based on the operation mode (read, program, or erase) without requiring external negative voltage generation. The circuit serves itself by internally generating the appropriate voltage levels, eliminating the need for complex external voltage generation hardware.
3Ease of manufacture
If standard CMOS technology is used for memory integration, then low cost price is achieved, but the ability to apply high erase or programming voltage without high-voltage transistors is limited
Solution Approach 1:
The mechanical/transistor-based high-voltage generation approach is replaced with an electronic voltage translation circuit. This substitution allows standard CMOS technology to be used while still achieving the necessary high voltage levels for erase and programming operations, maintaining both low cost and high reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the efficient application of high erase/programming voltages and low read voltages to phase change memory cells, simplifying the memory structure and reducing production costs while maintaining accurate voltage control.
Implementation Method 1
This state change is remnant and comes with a change in the electrical properties of the memory point. In a first so-called amorphous phase, the material has a high electrical resistivity, and in a second so-called crystalline phase the material has a low electrical resistivity.
Implementation Method 2
Phase change memory points comprise of a material which can change physical state under the effect of an electric signal, and more precisely under the effect of a temperature rise caused by an electric current passing through it (Joule effect).
Data Source
AI summary
An integrated circuit includes a non-volatile memory having memory cells, a memory cell selection circuit having selection blocks, a first device supplying a first voltage applicable to memory cells, a second device supplying a second voltage applicable to memory cells. Each memory cell selection block includes a first selection sub-block to link the memory cell to the first device and a second selection sub-block to link the memory cell to the second device. The first sub-block includes MOS transistors of a first type of conductivity, and the second sub-block includes MOS transistors of a second type of conductivity. Application may be particularly but not exclusively to phase change memories.