Reconfigurable Processing Units in Non-Volatile Memory

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Solution Overview

Problem

The Von Neumann bottleneck limits the speed of data transfer from non-volatile memory to volatile memory for data manipulation, restricting overall processing speed due to shared memory bus constraints.

Innovation Solution

A computing system with reconfigurable processing units associated with non-volatile memory, where data manipulation occurs in-place, and instruction sets are dynamically optimized based on usage frequency to enhance processing efficiency and reduce power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is transferred from non-volatile memory to volatile memory for manipulation, then data processing can be performed, but the speed is limited by hardware bandwidth (Von Neumann bottleneck)

Engineering Contradiction:
Improvedata processing speedVSAvoidoverall system throughput
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The patent merges the memory storage function and data processing function into a single integrated structure. Processing units are embedded within the non-volatile memory array, allowing data to be manipulated in-place without being transferred to separate volatile memory. This eliminates the Von Neumann bottleneck by combining what were previously separate components into a unified memory-processing system.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a new architectural dimension by moving processing capabilities directly into the memory fabric. Instead of the traditional sequential flow (memory → processor → memory), the system enables parallel in-place processing within the memory array, creating a multi-dimensional data access and processing model that bypasses traditional bandwidth limitations.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If processing units are made reconfigurable to optimize for frequently used instruction sets, then processing efficiency increases, but device complexity increases

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidprocessing unit configuration complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The processing units are designed to be dynamically reconfigurable based on the workload characteristics. The system monitors instruction set usage frequencies and automatically reconfigures the processing units to match the most commonly used operations. This dynamic adaptation allows the system to optimize processing efficiency for different workloads without requiring manual intervention or complex fixed architecture.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system implements self-service through automatic monitoring and reconfiguration of processing units. The memory controller tracks instruction set usage patterns and autonomously determines when and how to reconfigure processing units, eliminating the need for external control or complex configuration management. The system serves itself by adapting to workload demands without additional complexity in the control interface.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10114795B2Processor in non-volatile storage memory
Publication Date: 2018.10.30 SANDISK TECHNOLOGIES LLC
  • US10114795B2 patent drawing
  • US10114795B2 patent drawing
  • US10114795B2 patent drawing

AI summary

In one example, a device includes a non-volatile memory divided into a plurality of selectable locations, wherein the selectable locations are grouped into a plurality of data lines; one or more processing units (PUs) coupled to the non-volatile memory, each of the PUs associated with a data line of the plurality of data lines, the one or more processing units comprising one or more reconfigurable PUs, the one or more PUs configured to: manipulate, based on one or more instruction sets, data in an associated data line to generate results that are stored in selectable locations of the associated data line reserved to store results of the manipulation; determine which of the instruction sets are most frequently used by the one or more PUs to manipulate data; and reconfigure the one or more reconfigurable PUs to manipulate data using the determined most frequently used instruction sets.