Memory Subsystem Autocal Error Recovery via Offset Read Level Calibration
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Solution Overview
Problem
Flash memory devices, particularly NAND-based, experience bit errors due to shifts in threshold voltages over time, which can exceed the correction capacity of error correcting codes, leading to inefficient data retrieval from affected memory regions.
Innovation Solution
A memory system with calibration circuitry that measures performance characteristics using offset read level test signals to determine read level offset values, updating the current read level signals to account for threshold voltage shifts, thereby reducing bit errors and extending the memory device's lifespan.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correcting code (ECC) techniques are employed to detect and correct bit errors, then bit error correction capability is improved, but the correction capacity is limited and eventually exceeded as more electrons are trapped in tunnel oxide layers
Solution Approach 1:
The patent performs read level calibration in advance to determine optimal read levels before actual data retrieval operations. By pre-calibrating the read levels and storing calibration values, the system prepares compensation parameters ahead of time, enabling it to handle threshold voltage shifts more effectively when they occur during normal operation.
Solution Approach 2:
The patent dynamically adjusts read level parameters by applying calibration values to compensate for threshold voltage shifts. Instead of changing the physical structure or ECC code capacity, the system modifies the electrical read level parameters to adapt to aging effects, thereby extending the effective correction capacity beyond what fixed ECC codes can provide.
2Productivity
If memory devices operate over multiple erase and write cycles, then storage capacity and write speed are improved, but threshold voltages of memory cells change over time causing bit errors
Solution Approach 1:
The patent implements a feedback mechanism where read level calibration is performed periodically or on-demand to detect threshold voltage shifts. The calibration results are used to update read level compensation values, which are then applied in subsequent read operations. This closed-loop feedback allows the system to continuously adapt to aging effects while maintaining high write speed performance.
Solution Approach 2:
The patent employs periodic read level calibration operations to refresh compensation values at intervals. Rather than attempting to prevent threshold voltage changes during normal high-speed write operations, the system periodically recalibrates to account for accumulated aging effects, allowing sustained productivity while managing reliability degradation.
3Quantity of substance
If the number of memory cells with unreadable data states increases beyond ECC correction capacity, then data retrieval efficiency deteriorates, but the memory device can still physically store data
Solution Approach 1:
The patent introduces calibration values as an intermediary layer between the physical memory cells and the ECC correction mechanism. These calibration values serve as compensation parameters that adjust read levels to recover data from cells that would otherwise be unreadable. This intermediary approach extends the effective range of ECC correction without modifying the ECC code structure or reducing storage capacity.
Data Source
AI summary
Several embodiments of memory devices and systems with offset memory component automatic calibration error recovery are disclosed herein. In one embodiment, a system includes at least one memory region and calibration circuitry. The memory region has memory cells that read out data states in response to application of a current read level signal. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to one or more of a plurality of offset read level test signals, including a base offset read level test signal. The base offset read level test signal is offset from the current read level signal by a predetermined value. The calibration circuitry is further configured to output the determined read level offset value.