Narrowing Erase Threshold Voltage Distribution in Non-Volatile Memory
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Solution Overview
Problem
Process variations during manufacturing lead to differences in erase depth among non-volatile memory cells, resulting in deeper and wider erased threshold voltage distributions, which can cause programming errors, data retention issues, and interference from neighbor word lines.
Innovation Solution
A process is implemented to identify and differentiate between bit lines connected to memory cells that are and are not erased past a lower limit, applying programming to the former while inhibiting it for the latter to achieve a shallow and tight erased threshold voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard erase process is applied to non-volatile memory cells, then erase operation is completed, but erased threshold voltage distribution becomes deeper and wider due to process variations
Solution Approach 1:
The memory array is divided into multiple sub-arrays, and the erase operation is segmented into multiple passes. Each pass erases a subset of memory cells, allowing differential verification to identify and correct over-erased cells. This segmentation enables precise control over the erase depth distribution across the entire memory array.
Solution Approach 2:
The invention applies local quality by performing differential verification on specific subsets of memory cells (those connected to even versus odd word lines) and applying targeted programming pulses only to cells that require correction. This localized approach ensures that each cell receives the appropriate amount of programming to achieve uniform erase depth without affecting other cells.
2Productivity
If erase process is performed on memory cells, then data is cleared, but programming errors occur due to over-erasure beyond lower limit
Solution Approach 1:
The invention implements feedback through differential verification, where the threshold voltage of each memory cell is measured and compared against a reference. Based on this feedback, the system determines whether additional programming pulses are needed to correct over-erased cells, ensuring accurate programming without introducing errors.
Solution Approach 2:
The erase operation is performed as a preliminary action followed by a correction phase. The initial erase clears the data, and then differential verification identifies over-erased cells that require corrective programming. This two-stage approach ensures that productivity is maintained while programming accuracy is improved.
3Reliability
If memory cells are erased deeply, then erase operation is thorough, but interference from neighbor word lines increases
Solution Approach 1:
The invention applies partial action by erasing memory cells to a sufficient depth rather than excessive depth. Through differential verification, the system determines the precise amount of programming needed for each cell, avoiding over-erasure that would cause interference with neighboring word lines while still achieving thorough erase completeness.
4Productivity
If standard programming is applied to all memory cells, then data is written, but data retention issues occur due to process variations
Solution Approach 1:
The invention applies local quality by performing differential verification on specific subsets of memory cells and applying targeted programming pulses only to cells that require correction. This localized approach ensures that each cell receives the appropriate amount of programming to achieve uniform erase depth without affecting other cells.
Data Source
AI summary
In a non-volatile memory, to achieve a shallow and tight erased threshold voltage distribution, a process is performed that includes erasing a group of non-volatile memory cells, identifying a first set of the bit lines that are connected to non-volatile memory cells of the group that are erased past a lower limit for erased non-volatile memory cells and identifying a second set of the bit lines that are connected to non-volatile memory cells of the group that are not erased past the lower limit for erased non-volatile memory cells, and applying programming to non-volatile memory cells connected to the first set of bit lines while inhibiting programming for non-volatile memory cells connected to the second set of bit lines.