Deck Select Transistor 3D Cross-Point Memory Density
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Solution Overview
Problem
Increasing the number of memory cells in a 3-D cross point memory array proportionally increases the number of decoder transistors required, leading to a larger footprint and challenging the goal of high-density memory arrays for a given die size.
Innovation Solution
Integrating deck select transistors within each word line and bit line of a deck, and collectively coupling vertically spaced word lines and bit lines across multiple decks with interconnect vias, reducing the number of decoder transistors needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells in a 3-D cross point memory array is increased, then memory density is improved, but the number of decoder transistors increases proportionally, worsening the decoder transistor footprint
Solution Approach 1:
The patent combines multiple vertically-spaced word lines from different decks into a single integrated word line structure. This merging allows one decoder transistor to control multiple decks simultaneously, reducing the total number of decoder transistors required while maintaining the ability to access individual memory cells across increased memory density
Solution Approach 2:
The integrated word line structure serves multiple functions: it acts as a selector for individual memory cells within a deck, provides common control across multiple decks, and enables scalable memory expansion. This multi-functionality allows the same decoder transistor to serve multiple decks, reducing the proportional increase in decoder transistors as memory density increases
Data Source
Figure 1
Figure 2A~2D
Figure 3A~3C
AI summary
The disclosed memory device structure (100) includes a first plurality of line structures (102), where each line structure includes a first transistor channel (108), a second plurality of line structures (112) substantially orthogonal to the first plurality of line structures, where each line structure includes a second transistor channel (118), and a memory cell (122) at each cross-point between the first plurality of line structures and the second plurality of line structures. In particular, the structure is a three-dimensional cross-point array of resistive memory cells with FET deck selection transistors (101A) located at each deck level (128).