3D Dynamic Flash Memory Pillar With Ring Dielectric for Charge Retention
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Solution Overview
Problem
Current dynamic random-access memory (DRAM) technologies face challenges with increased current leakage, power consumption, and decreased retention times, especially at high temperatures, and single transistor capacitor-free DRAM devices require improvements in manufacturability and operation.
Innovation Solution
A three-dimensional (3D) memory device design featuring a memory cell with a pillar, insulating layer, and gate contacts that dynamically adjust to increase retention times, reduce leakage current, and enhance charge density, using different doping concentrations and materials to optimize the floating body effect and reduce parasitic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If 1T1C DRAM devices use smaller node capacitors to retain charge, then charge retention capability is improved, but current leakage increases and manufacturing difficulty increases
Solution Approach 1:
The patent transitions from planar 2D capacitor structures to three-dimensional vertical pillar structures. The pillar extends vertically through multiple insulating layers and gate contacts, utilizing the third dimension (height) to increase charge storage capacity without increasing lateral footprint. This dimensional change enables better charge retention while maintaining manufacturability through vertical stacking rather than lateral scaling.
Solution Approach 2:
The memory device employs composite material structures including alternating epitaxial layers of silicon and silicon germanium, combined with multiple dielectric materials (oxide, nitride, oxynitride) in the insulating layers. These composite materials provide optimized electrical properties for charge retention while managing stress and leakage currents, resolving the contradiction between retention capability and manufacturing complexity.
2Temperature
If DRAM operates at high temperature, then processing capability is improved, but retention time decreases
Solution Approach 1:
The patent modifies physical and chemical parameters including doping concentrations in different regions, thickness ratios of alternating epitaxial layers, and composition gradients in silicon-silicon germanium structures. These parameter changes optimize the balance between thermal processing capability and charge retention, enabling the device to maintain performance at elevated temperatures by adjusting material properties rather than operating conditions.
3Device complexity
If capacitor-free DRAM is used to simplify structure, then device complexity is reduced, but integration and operation optimization is needed
Solution Approach 1:
The patent merges the capacitor and transistor functions into a unified vertical pillar structure. The pillar serves dual purposes as both the charge storage element (replacing the traditional capacitor) and the active region for transistor operation. This consolidation eliminates separate capacitor components and reduces overall device complexity while maintaining functionality through the floating body effect in the vertical structure.
4Reliability
If insulating layers are added to isolate channel and body, then charge retention is improved, but manufacturing steps increase
Solution Approach 1:
The patent employs periodic alternating layers of oxide and nitride dielectrics in the insulating structure. This periodic stacking of different material types provides both electrical isolation and mechanical stress management in a repeating pattern that can be deposited using standard cyclic deposition processes. The periodic structure achieves superior charge retention through multiple isolation interfaces while utilizing existing manufacturing capabilities for layered dielectric deposition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly increases retention times, decreases refresh rates, and improves manufacturing efficiency while maintaining low leakage current and power consumption, offering enhanced performance and reliability compared to traditional DRAM devices.
Implementation Method 1
The annular dielectric layer can be within a portion of the pillar and between the pillar and the insulating layer. The annular dielectric layer can be configured to increase a retention time in the pillar.
Implementation Method 2
the pillar can be configured to store an electrical charge. Different doping concentrations in a memory cell can increase a floating body effect.
Data Source
AI summary
A three-dimensional (3D) memory device includes a memory cell, a top contact coupled to the memory cell, and a bottom contact coupled to the memory cell. The memory cell can include a pillar, an insulating layer surrounding the pillar, a first gate contact coupled to a word line, a second gate contact coupled to a plate line, and an annular dielectric layer within a portion of the pillar. The annular dielectric layer can increase a retention time of electrical charge in the pillar. The 3D memory device can utilize dynamic flash memory (DFM), increase retention times, decrease refresh rates, increase a floating body effect, decrease manufacturing defects, decrease leakage current, decrease junction current, decrease power consumption, increase an upper limit of charge density in the pillar, dynamically adjust a length of the plate line, and decrease parasitic resistance.