3D Flash Memory Tiered Wiring for CSL-GBL Spacing
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Solution Overview
Problem
Three-dimensional NAND flash memory faces challenges in integration and wiring efficiency due to spacing constraints between the common source line and global bit lines.
Innovation Solution
A memory device design incorporating a common source line and wider pitch in the back end of line (BEOL) process, which increases spacing between the common source line and global bit lines, reducing the CSL/GBL short rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a three-dimensional NAND flash memory structure is used to enhance integration, then area utilization is improved, but spacing constraints between common source line and global bit lines occur
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture, where memory cells are arranged vertically across multiple tiers. This dimensional change allows significant area utilization improvement while managing wiring complexity through vertical stacking rather than horizontal expansion, thereby resolving the spacing constraints in the horizontal plane.
Solution Approach 2:
The memory device is divided into multiple tiers (first tier with first transistors, second tier with composite stack structure, third tier with local bit lines and local source lines, fourth tier with global bit lines and common source line). This segmentation separates different wiring layers and transistor groups into distinct vertical levels, allowing independent optimization of spacing and routing in each tier while maintaining overall integration.
2Reliability
If wider pitch is provided for the back end of line process, then CSL/GBL short rate is reduced, but wiring complexity increases
Solution Approach 1:
The patent resolves wiring complexity by moving CSL and GBL connections to different vertical tiers rather than routing them in the same horizontal plane. The common source line is positioned in the fourth tier while global bit lines are distributed across multiple tiers, utilizing the vertical dimension to achieve wider effective pitch and reduce short rates without requiring excessive horizontal wiring space.
Solution Approach 2:
Local bit lines and local source lines in the third tier serve as intermediary connections between the first tier transistors and the global bit lines/common source line in the fourth tier. This intermediary layer simplifies the overall wiring architecture by breaking down direct CSL-GBL connections into staged connections, reducing the risk of shorts while maintaining wiring efficiency.
Data Source
AI summary
A memory device includes a substrate and first to fourth tiers. The first tier is located on the substrate and includes first transistors and second transistors. The first transistors includes multiple groups. The second tier includes a composite stack structure. The third tier includes local bit lines and local source lines. Each of the local bit lines is connected to a first terminal of one of the first transistors. Each of the local source lines is connected to a first terminal of one of the second transistors. The fourth tier includes multiple global bit lines and a common source line. Each of the global bit lines is connected to second terminals of the first transistors in one of the groups. The common source line is connected to a second terminal of each of the second transistors. Embodiments of the present disclosure may be applied to a 3D AND flash memory.