3D Flash Memory TSV Layout for Higher Integration Density
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Solution Overview
Problem
Conventional three-dimensional flash memories face issues with low integration density, high manufacturing costs, and complex source line processes due to the stack structure of memory cell and peripheral circuit chips, as well as poor integration resulting from drain line connections outside the memory cell string area.
Innovation Solution
A three-dimensional flash memory design that connects memory cell and peripheral circuit chips using Through Silicon Vias (TSVs) and incorporates a buried source line in the substrate, allowing for separate manufacturing processes and improved integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a stack structure of one memory cell string chip and one peripheral circuit chip is used, then the three-dimensional flash memory can be constructed, but the integration density is not relatively high
Solution Approach 1:
The patent divides the memory device into separate functional modules: memory cell string chips and peripheral circuit chips are manufactured independently and then connected through TSVs. This segmentation allows each module to be optimized separately while achieving high integration density when assembled together.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional integration by stacking memory cell string chips and peripheral circuit chips in vertical layers, connected via TSVs. This dimensional change enables significantly higher integration density compared to conventional two-dimensional layouts.
2Adaptability or versatility
If the memory cell string chip includes peripheral circuits in the substrate, then the chip can be self-contained, but the manufacturing process cost is high
Solution Approach 1:
The patent separates the memory cell string chip and peripheral circuit chip into distinct manufacturing processes. The memory cell string chip focuses solely on memory cell formation, while the peripheral circuit chip handles control logic, reducing process complexity and cost for each individual chip.
Solution Approach 2:
TSVs serve as intermediaries connecting the memory cell string chip and peripheral circuit chip, enabling communication and data transfer between the separately manufactured chips without requiring integration of all circuits into a single substrate.
3Ease of operation
If the drain line connection is located outside the memory cell string area, then the connection can be established, but the integration is poor
Solution Approach 1:
The patent moves the drain line connection from a planar configuration outside the memory cell string area to a three-dimensional configuration where TSVs provide vertical connections through the substrate, achieving compact integration within the memory cell string footprint.
Data Source
AI summary
A through silicon via (TSV)-based three-dimensional flash memory having a high degree of integration comprises: at least one memory cell string chip including a plurality of memory cell strings; and a peripheral circuit chip including at least one peripheral circuit, wherein the peripheral circuit chip is arranged below the at least one memory cell string chip and is connected to the at least one memory cell string chip by using at least one TSV. The at least one memory cell string chip includes the plurality of memory cell strings, and the peripheral circuit chip is connected to the at least one peripheral circuit. The peripheral circuit chip is connected to the at least one memory cell string chip by using the at least one TSV extending through the at least one memory cell string chip.