3D Flip-Flop Transistor Partitioning for Clock Skew Reduction
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Solution Overview
Problem
Monolithic three-dimensional integrated circuits (3DICs) face challenges with clock skew due to process variations between layers, leading to unacceptable setup times, hold times, and clock-to-q margins, exacerbated by software-driven chip layout design.
Innovation Solution
The 3DIC design splits flip-flops across at least two tiers with transistor partitioning, keeping clock-related devices on the same tier to minimize process variations, using monolithic intertier vias for connectivity, and optionally varying transistor types between tiers for optimized performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If flip-flops are placed across multiple tiers in monolithic 3DIC, then area utilization and miniaturization are improved, but clock skew and process variations worsen
Solution Approach 1:
The flip-flop is segmented into two parts: clock-related devices (master latch, slave latch, clock circuit) are placed on one tier while data input circuitry is placed on another tier. This segmentation allows each part to be optimized for its specific function while managing the trade-off between area utilization and clock skew.
Solution Approach 2:
The patent transitions from traditional two-dimensional placement to three-dimensional tiered placement. By utilizing the vertical dimension in monolithic 3DIC, the design achieves better area utilization while carefully managing inter-tier connections to control clock skew through precise synchronization mechanisms.
2Area of stationary object
If clock-related devices are distributed across different tiers, then area efficiency is improved, but setup times and hold times deteriorate
Solution Approach 1:
The flip-flop is segmented into two parts: clock-related devices (master latch, slave latch, clock circuit) are placed on one tier while data input circuitry is placed on another tier. This segmentation allows each part to be optimized for its specific function while managing the trade-off between area utilization and clock skew.
Solution Approach 2:
Synchronization mechanisms act as intermediaries between tiers to coordinate clock signals and data signals. These intermediaries ensure that setup times and hold times are maintained despite the physical separation of clock-related devices and data input circuitry across different tiers.
3Manufacturing precision
If transistor partitioning is used to keep clock devices on the same tier, then clock skew is reduced, but device complexity increases
Solution Approach 1:
The flip-flop is segmented into two parts: clock-related devices (master latch, slave latch, clock circuit) are placed on one tier while data input circuitry is placed on another tier. This segmentation allows each part to be optimized for its specific function while managing the trade-off between area utilization and clock skew.
Data Source
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AI summary
Monolithic three dimensional (3D) flip-flops with minimal clock skew and related systems and methods are disclosed. The present disclosure provides a 3D integrated circuit (IC) (3DIC) that has a flop spread across at least two tiers of the 3DIC. The flop is split across tiers with transistor partitioning in such a way that keeps all the clock related devices at the same tier, thus potentially giving better setup, hold and clock-to-q margin. In particular, a first tier of the 3DIC has the master latch, slave latch, and clock circuit. A second tier has the input circuit and the output circuit.